76 lines
3.2 KiB
XML
76 lines
3.2 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<database xmlns="http://nouveau.freedesktop.org/"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
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<import file="freedreno_copyright.xml"/>
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<!-- These registers are used on the DSI hosts v2 to control PHY -->
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<domain name="DSI_PHY_8610" width="32">
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<reg32 offset="0x00200" name="PHY_PLL_CTRL_0">
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<bitfield name="ENABLE" pos="0" type="boolean"/>
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</reg32>
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<reg32 offset="0x00204" name="PHY_PLL_CTRL_1"/>
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<reg32 offset="0x00208" name="PHY_PLL_CTRL_2"/>
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<reg32 offset="0x0020c" name="PHY_PLL_CTRL_3"/>
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<reg32 offset="0x00210" name="PHY_PLL_CTRL_4"/>
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<reg32 offset="0x00214" name="PHY_PLL_CTRL_5"/>
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<reg32 offset="0x00218" name="PHY_PLL_CTRL_6"/>
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<reg32 offset="0x0021c" name="PHY_PLL_CTRL_7"/>
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<reg32 offset="0x00220" name="PHY_PLL_CTRL_8"/>
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<reg32 offset="0x00224" name="PHY_PLL_CTRL_9"/>
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<reg32 offset="0x00228" name="PHY_PLL_CTRL_10"/>
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<reg32 offset="0x0022c" name="PHY_PLL_CTRL_11"/>
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<reg32 offset="0x00230" name="PHY_PLL_CTRL_12"/>
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<reg32 offset="0x00234" name="PHY_PLL_CTRL_13"/>
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<reg32 offset="0x00238" name="PHY_PLL_CTRL_14"/>
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<reg32 offset="0x0023c" name="PHY_PLL_CTRL_15"/>
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<reg32 offset="0x00240" name="PHY_PLL_CTRL_16"/>
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<reg32 offset="0x00244" name="PHY_PLL_CTRL_17"/>
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<reg32 offset="0x00248" name="PHY_PLL_CTRL_18"/>
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<reg32 offset="0x0024c" name="PHY_PLL_CTRL_19"/>
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<reg32 offset="0x00250" name="PHY_PLL_CTRL_20"/>
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<reg32 offset="0x00280" name="PHY_PLL_STATUS">
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<bitfield name="PLL_BUSY" pos="0" type="boolean"/>
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</reg32>
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</domain>
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<domain name="DSI_PHY_8x60" width="32">
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<reg32 offset="0x00258" name="PHY_TPA_CTRL_1"/>
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<reg32 offset="0x0025c" name="PHY_TPA_CTRL_2"/>
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<reg32 offset="0x00260" name="PHY_TIMING_CTRL_0"/>
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<reg32 offset="0x00264" name="PHY_TIMING_CTRL_1"/>
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<reg32 offset="0x00268" name="PHY_TIMING_CTRL_2"/>
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<reg32 offset="0x0026c" name="PHY_TIMING_CTRL_3"/>
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<reg32 offset="0x00270" name="PHY_TIMING_CTRL_4"/>
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<reg32 offset="0x00274" name="PHY_TIMING_CTRL_5"/>
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<reg32 offset="0x00278" name="PHY_TIMING_CTRL_6"/>
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<reg32 offset="0x0027c" name="PHY_TIMING_CTRL_7"/>
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<reg32 offset="0x00280" name="PHY_TIMING_CTRL_8"/>
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<reg32 offset="0x00284" name="PHY_TIMING_CTRL_9"/>
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<reg32 offset="0x00288" name="PHY_TIMING_CTRL_10"/>
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<reg32 offset="0x0028c" name="PHY_TIMING_CTRL_11"/>
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<reg32 offset="0x00290" name="PHY_CTRL_0"/>
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<reg32 offset="0x00294" name="PHY_CTRL_1"/>
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<reg32 offset="0x00298" name="PHY_CTRL_2"/>
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<reg32 offset="0x0029c" name="PHY_CTRL_3"/>
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<reg32 offset="0x002a0" name="PHY_STRENGTH_0"/>
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<reg32 offset="0x002a4" name="PHY_STRENGTH_1"/>
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<reg32 offset="0x002a8" name="PHY_STRENGTH_2"/>
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<reg32 offset="0x002ac" name="PHY_STRENGTH_3"/>
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<reg32 offset="0x002cc" name="PHY_REGULATOR_CTRL_0"/>
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<reg32 offset="0x002d0" name="PHY_REGULATOR_CTRL_1"/>
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<reg32 offset="0x002d4" name="PHY_REGULATOR_CTRL_2"/>
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<reg32 offset="0x002d8" name="PHY_REGULATOR_CTRL_3"/>
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<reg32 offset="0x002dc" name="PHY_REGULATOR_CTRL_4"/>
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<reg32 offset="0x000f0" name="PHY_CAL_HW_TRIGGER"/>
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<reg32 offset="0x000f4" name="PHY_CAL_CTRL"/>
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<reg32 offset="0x000fc" name="PHY_CAL_STATUS">
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<bitfield name="CAL_BUSY" pos="28" type="boolean"/>
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</reg32>
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</domain>
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</database>
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