233 lines
8.0 KiB
C
233 lines
8.0 KiB
C
/*
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* Copyright © 2018 Valve Corporation
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* Copyright © 2017 Red Hat
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "vtn_private.h"
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#include "GLSL.ext.AMD.h"
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bool
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vtn_handle_amd_gcn_shader_instruction(struct vtn_builder *b, SpvOp ext_opcode,
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const uint32_t *w, unsigned count)
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{
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nir_ssa_def *def;
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switch ((enum GcnShaderAMD)ext_opcode) {
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case CubeFaceIndexAMD:
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def = nir_cube_face_index_amd(&b->nb, vtn_get_nir_ssa(b, w[5]));
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break;
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case CubeFaceCoordAMD:
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def = nir_cube_face_coord_amd(&b->nb, vtn_get_nir_ssa(b, w[5]));
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break;
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case TimeAMD: {
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def = nir_pack_64_2x32(&b->nb, nir_shader_clock(&b->nb, NIR_SCOPE_SUBGROUP));
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break;
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}
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default:
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unreachable("Invalid opcode");
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}
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vtn_push_nir_ssa(b, w[2], def);
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return true;
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}
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bool
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vtn_handle_amd_shader_ballot_instruction(struct vtn_builder *b, SpvOp ext_opcode,
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const uint32_t *w, unsigned count)
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{
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unsigned num_args;
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nir_intrinsic_op op;
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switch ((enum ShaderBallotAMD)ext_opcode) {
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case SwizzleInvocationsAMD:
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num_args = 1;
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op = nir_intrinsic_quad_swizzle_amd;
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break;
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case SwizzleInvocationsMaskedAMD:
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num_args = 1;
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op = nir_intrinsic_masked_swizzle_amd;
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break;
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case WriteInvocationAMD:
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num_args = 3;
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op = nir_intrinsic_write_invocation_amd;
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break;
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case MbcntAMD:
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num_args = 1;
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op = nir_intrinsic_mbcnt_amd;
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break;
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default:
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unreachable("Invalid opcode");
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}
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const struct glsl_type *dest_type = vtn_get_type(b, w[1])->type;
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nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(b->nb.shader, op);
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nir_ssa_dest_init_for_type(&intrin->instr, &intrin->dest, dest_type, NULL);
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if (nir_intrinsic_infos[op].src_components[0] == 0)
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intrin->num_components = intrin->dest.ssa.num_components;
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for (unsigned i = 0; i < num_args; i++)
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intrin->src[i] = nir_src_for_ssa(vtn_get_nir_ssa(b, w[i + 5]));
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if (intrin->intrinsic == nir_intrinsic_quad_swizzle_amd) {
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struct vtn_value *val = vtn_value(b, w[6], vtn_value_type_constant);
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unsigned mask = val->constant->values[0].u32 |
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val->constant->values[1].u32 << 2 |
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val->constant->values[2].u32 << 4 |
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val->constant->values[3].u32 << 6;
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nir_intrinsic_set_swizzle_mask(intrin, mask);
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} else if (intrin->intrinsic == nir_intrinsic_masked_swizzle_amd) {
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struct vtn_value *val = vtn_value(b, w[6], vtn_value_type_constant);
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unsigned mask = val->constant->values[0].u32 |
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val->constant->values[1].u32 << 5 |
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val->constant->values[2].u32 << 10;
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nir_intrinsic_set_swizzle_mask(intrin, mask);
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} else if (intrin->intrinsic == nir_intrinsic_mbcnt_amd) {
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/* The v_mbcnt instruction has an additional source that is added to the result.
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* This is exposed by the NIR intrinsic but not by SPIR-V, so we add zero here.
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*/
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intrin->src[1] = nir_src_for_ssa(nir_imm_int(&b->nb, 0));
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}
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nir_builder_instr_insert(&b->nb, &intrin->instr);
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vtn_push_nir_ssa(b, w[2], &intrin->dest.ssa);
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return true;
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}
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bool
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vtn_handle_amd_shader_trinary_minmax_instruction(struct vtn_builder *b, SpvOp ext_opcode,
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const uint32_t *w, unsigned count)
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{
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struct nir_builder *nb = &b->nb;
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unsigned num_inputs = count - 5;
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assert(num_inputs == 3);
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nir_ssa_def *src[3] = { NULL, };
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for (unsigned i = 0; i < num_inputs; i++)
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src[i] = vtn_get_nir_ssa(b, w[i + 5]);
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/* place constants at src[1-2] for easier constant-folding */
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for (unsigned i = 1; i <= 2; i++) {
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if (nir_src_as_const_value(nir_src_for_ssa(src[0]))) {
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nir_ssa_def* tmp = src[i];
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src[i] = src[0];
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src[0] = tmp;
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}
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}
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nir_ssa_def *def;
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switch ((enum ShaderTrinaryMinMaxAMD)ext_opcode) {
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case FMin3AMD:
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def = nir_fmin(nb, src[0], nir_fmin(nb, src[1], src[2]));
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break;
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case UMin3AMD:
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def = nir_umin(nb, src[0], nir_umin(nb, src[1], src[2]));
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break;
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case SMin3AMD:
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def = nir_imin(nb, src[0], nir_imin(nb, src[1], src[2]));
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break;
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case FMax3AMD:
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def = nir_fmax(nb, src[0], nir_fmax(nb, src[1], src[2]));
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break;
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case UMax3AMD:
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def = nir_umax(nb, src[0], nir_umax(nb, src[1], src[2]));
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break;
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case SMax3AMD:
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def = nir_imax(nb, src[0], nir_imax(nb, src[1], src[2]));
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break;
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case FMid3AMD:
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def = nir_fmin(nb, nir_fmax(nb, src[0], nir_fmin(nb, src[1], src[2])),
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nir_fmax(nb, src[1], src[2]));
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break;
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case UMid3AMD:
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def = nir_umin(nb, nir_umax(nb, src[0], nir_umin(nb, src[1], src[2])),
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nir_umax(nb, src[1], src[2]));
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break;
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case SMid3AMD:
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def = nir_imin(nb, nir_imax(nb, src[0], nir_imin(nb, src[1], src[2])),
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nir_imax(nb, src[1], src[2]));
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break;
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default:
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unreachable("unknown opcode\n");
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break;
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}
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vtn_push_nir_ssa(b, w[2], def);
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return true;
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}
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bool
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vtn_handle_amd_shader_explicit_vertex_parameter_instruction(struct vtn_builder *b, SpvOp ext_opcode,
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const uint32_t *w, unsigned count)
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{
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nir_intrinsic_op op;
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switch ((enum ShaderExplicitVertexParameterAMD)ext_opcode) {
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case InterpolateAtVertexAMD:
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op = nir_intrinsic_interp_deref_at_vertex;
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break;
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default:
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unreachable("unknown opcode");
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}
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nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(b->nb.shader, op);
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struct vtn_pointer *ptr =
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vtn_value(b, w[5], vtn_value_type_pointer)->pointer;
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nir_deref_instr *deref = vtn_pointer_to_deref(b, ptr);
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/* If the value we are interpolating has an index into a vector then
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* interpolate the vector and index the result of that instead. This is
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* necessary because the index will get generated as a series of nir_bcsel
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* instructions so it would no longer be an input variable.
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*/
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const bool vec_array_deref = deref->deref_type == nir_deref_type_array &&
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glsl_type_is_vector(nir_deref_instr_parent(deref)->type);
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nir_deref_instr *vec_deref = NULL;
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if (vec_array_deref) {
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vec_deref = deref;
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deref = nir_deref_instr_parent(deref);
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}
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intrin->src[0] = nir_src_for_ssa(&deref->dest.ssa);
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intrin->src[1] = nir_src_for_ssa(vtn_get_nir_ssa(b, w[6]));
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intrin->num_components = glsl_get_vector_elements(deref->type);
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nir_ssa_dest_init(&intrin->instr, &intrin->dest,
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glsl_get_vector_elements(deref->type),
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glsl_get_bit_size(deref->type), NULL);
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nir_builder_instr_insert(&b->nb, &intrin->instr);
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nir_ssa_def *def;
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if (vec_array_deref) {
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assert(vec_deref);
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def = nir_vector_extract(&b->nb, &intrin->dest.ssa,
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vec_deref->arr.index.ssa);
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} else {
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def = &intrin->dest.ssa;
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}
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vtn_push_nir_ssa(b, w[2], def);
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return true;
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}
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