499 lines
17 KiB
C++
499 lines
17 KiB
C++
/*
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* Copyright © 2021 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "aco_builder.h"
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#include "aco_ir.h"
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#include <algorithm>
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#include <array>
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#include <bitset>
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#include <vector>
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namespace aco {
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namespace {
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constexpr const size_t max_reg_cnt = 512;
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struct Idx {
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bool operator==(const Idx& other) const { return block == other.block && instr == other.instr; }
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bool operator!=(const Idx& other) const { return !operator==(other); }
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bool found() const { return block != UINT32_MAX; }
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uint32_t block;
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uint32_t instr;
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};
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Idx not_written_in_block{UINT32_MAX, 0};
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Idx clobbered{UINT32_MAX, 1};
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Idx const_or_undef{UINT32_MAX, 2};
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Idx written_by_multiple_instrs{UINT32_MAX, 3};
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struct pr_opt_ctx {
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Program* program;
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Block* current_block;
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uint32_t current_instr_idx;
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std::vector<uint16_t> uses;
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std::vector<std::array<Idx, max_reg_cnt>> instr_idx_by_regs;
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void reset_block(Block* block)
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{
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current_block = block;
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current_instr_idx = 0;
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if ((block->kind & block_kind_loop_header) || block->linear_preds.empty()) {
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std::fill(instr_idx_by_regs[block->index].begin(), instr_idx_by_regs[block->index].end(),
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not_written_in_block);
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} else {
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unsigned first_pred = block->linear_preds[0];
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for (unsigned i = 0; i < max_reg_cnt; i++) {
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bool all_same = std::all_of(
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std::next(block->linear_preds.begin()), block->linear_preds.end(),
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[&](unsigned pred)
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{ return instr_idx_by_regs[pred][i] == instr_idx_by_regs[first_pred][i]; });
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if (all_same)
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instr_idx_by_regs[block->index][i] = instr_idx_by_regs[first_pred][i];
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else
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instr_idx_by_regs[block->index][i] = not_written_in_block;
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}
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}
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}
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Instruction* get(Idx idx) { return program->blocks[idx.block].instructions[idx.instr].get(); }
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};
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void
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save_reg_writes(pr_opt_ctx& ctx, aco_ptr<Instruction>& instr)
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{
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for (const Definition& def : instr->definitions) {
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assert(def.regClass().type() != RegType::sgpr || def.physReg().reg() <= 255);
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assert(def.regClass().type() != RegType::vgpr || def.physReg().reg() >= 256);
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unsigned dw_size = DIV_ROUND_UP(def.bytes(), 4u);
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unsigned r = def.physReg().reg();
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Idx idx{ctx.current_block->index, ctx.current_instr_idx};
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if (def.regClass().is_subdword())
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idx = clobbered;
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assert((r + dw_size) <= max_reg_cnt);
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assert(def.size() == dw_size || def.regClass().is_subdword());
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std::fill(ctx.instr_idx_by_regs[ctx.current_block->index].begin() + r,
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ctx.instr_idx_by_regs[ctx.current_block->index].begin() + r + dw_size, idx);
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}
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}
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Idx
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last_writer_idx(pr_opt_ctx& ctx, PhysReg physReg, RegClass rc)
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{
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/* Verify that all of the operand's registers are written by the same instruction. */
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assert(physReg.reg() < max_reg_cnt);
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Idx instr_idx = ctx.instr_idx_by_regs[ctx.current_block->index][physReg.reg()];
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unsigned dw_size = DIV_ROUND_UP(rc.bytes(), 4u);
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unsigned r = physReg.reg();
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bool all_same =
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std::all_of(ctx.instr_idx_by_regs[ctx.current_block->index].begin() + r,
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ctx.instr_idx_by_regs[ctx.current_block->index].begin() + r + dw_size,
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[instr_idx](Idx i) { return i == instr_idx; });
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return all_same ? instr_idx : written_by_multiple_instrs;
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}
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Idx
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last_writer_idx(pr_opt_ctx& ctx, const Operand& op)
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{
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if (op.isConstant() || op.isUndefined())
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return const_or_undef;
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assert(op.physReg().reg() < max_reg_cnt);
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Idx instr_idx = ctx.instr_idx_by_regs[ctx.current_block->index][op.physReg().reg()];
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#ifndef NDEBUG
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/* Debug mode: */
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instr_idx = last_writer_idx(ctx, op.physReg(), op.regClass());
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assert(instr_idx != written_by_multiple_instrs);
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#endif
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return instr_idx;
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}
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bool
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is_clobbered_since(pr_opt_ctx& ctx, PhysReg reg, RegClass rc, const Idx& idx)
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{
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/* If we didn't find an instruction, assume that the register is clobbered. */
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if (!idx.found())
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return true;
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/* TODO: We currently can't keep track of subdword registers. */
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if (rc.is_subdword())
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return true;
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unsigned begin_reg = reg.reg();
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unsigned end_reg = begin_reg + rc.size();
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unsigned current_block_idx = ctx.current_block->index;
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for (unsigned r = begin_reg; r < end_reg; ++r) {
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Idx& i = ctx.instr_idx_by_regs[current_block_idx][r];
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if (i == clobbered || i == written_by_multiple_instrs)
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return true;
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else if (i == not_written_in_block)
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continue;
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assert(i.found());
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if (i.block > idx.block || (i.block == idx.block && i.instr > idx.instr))
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return true;
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}
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return false;
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}
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template <typename T>
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bool
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is_clobbered_since(pr_opt_ctx& ctx, const T& t, const Idx& idx)
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{
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return is_clobbered_since(ctx, t.physReg(), t.regClass(), idx);
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}
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void
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try_apply_branch_vcc(pr_opt_ctx& ctx, aco_ptr<Instruction>& instr)
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{
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/* We are looking for the following pattern:
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*
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* vcc = ... ; last_vcc_wr
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* sX, scc = s_and_bXX vcc, exec ; op0_instr
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* (...vcc and exec must not be clobbered inbetween...)
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* s_cbranch_XX scc ; instr
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*
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* If possible, the above is optimized into:
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*
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* vcc = ... ; last_vcc_wr
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* s_cbranch_XX vcc ; instr modified to use vcc
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*/
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/* Don't try to optimize this on GFX6-7 because SMEM may corrupt the vccz bit. */
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if (ctx.program->gfx_level < GFX8)
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return;
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if (instr->format != Format::PSEUDO_BRANCH || instr->operands.size() == 0 ||
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instr->operands[0].physReg() != scc)
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return;
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Idx op0_instr_idx = last_writer_idx(ctx, instr->operands[0]);
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Idx last_vcc_wr_idx = last_writer_idx(ctx, vcc, ctx.program->lane_mask);
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/* We need to make sure:
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* - the instructions that wrote the operand register and VCC are both found
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* - the operand register used by the branch, and VCC were both written in the current block
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* - EXEC hasn't been clobbered since the last VCC write
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* - VCC hasn't been clobbered since the operand register was written
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* (ie. the last VCC writer precedes the op0 writer)
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*/
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if (!op0_instr_idx.found() || !last_vcc_wr_idx.found() ||
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op0_instr_idx.block != ctx.current_block->index ||
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last_vcc_wr_idx.block != ctx.current_block->index ||
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is_clobbered_since(ctx, exec, ctx.program->lane_mask, last_vcc_wr_idx) ||
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is_clobbered_since(ctx, vcc, ctx.program->lane_mask, op0_instr_idx))
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return;
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Instruction* op0_instr = ctx.get(op0_instr_idx);
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Instruction* last_vcc_wr = ctx.get(last_vcc_wr_idx);
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if ((op0_instr->opcode != aco_opcode::s_and_b64 /* wave64 */ &&
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op0_instr->opcode != aco_opcode::s_and_b32 /* wave32 */) ||
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op0_instr->operands[0].physReg() != vcc || op0_instr->operands[1].physReg() != exec ||
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!last_vcc_wr->isVOPC())
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return;
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assert(last_vcc_wr->definitions[0].tempId() == op0_instr->operands[0].tempId());
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/* Reduce the uses of the SCC def */
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ctx.uses[instr->operands[0].tempId()]--;
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/* Use VCC instead of SCC in the branch */
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instr->operands[0] = op0_instr->operands[0];
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}
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void
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try_optimize_scc_nocompare(pr_opt_ctx& ctx, aco_ptr<Instruction>& instr)
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{
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/* We are looking for the following pattern:
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*
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* s_bfe_u32 s0, s3, 0x40018 ; outputs SGPR and SCC if the SGPR != 0
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* s_cmp_eq_i32 s0, 0 ; comparison between the SGPR and 0
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* s_cbranch_scc0 BB3 ; use the result of the comparison, eg. branch or cselect
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*
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* If possible, the above is optimized into:
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*
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* s_bfe_u32 s0, s3, 0x40018 ; original instruction
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* s_cbranch_scc1 BB3 ; modified to use SCC directly rather than the SGPR with comparison
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*
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*/
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if (!instr->isSALU() && !instr->isBranch())
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return;
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if (instr->isSOPC() &&
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(instr->opcode == aco_opcode::s_cmp_eq_u32 || instr->opcode == aco_opcode::s_cmp_eq_i32 ||
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instr->opcode == aco_opcode::s_cmp_lg_u32 || instr->opcode == aco_opcode::s_cmp_lg_i32 ||
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instr->opcode == aco_opcode::s_cmp_eq_u64 || instr->opcode == aco_opcode::s_cmp_lg_u64) &&
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(instr->operands[0].constantEquals(0) || instr->operands[1].constantEquals(0)) &&
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(instr->operands[0].isTemp() || instr->operands[1].isTemp())) {
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/* Make sure the constant is always in operand 1 */
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if (instr->operands[0].isConstant())
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std::swap(instr->operands[0], instr->operands[1]);
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if (ctx.uses[instr->operands[0].tempId()] > 1)
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return;
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/* Make sure both SCC and Operand 0 are written by the same instruction. */
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Idx wr_idx = last_writer_idx(ctx, instr->operands[0]);
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Idx sccwr_idx = last_writer_idx(ctx, scc, s1);
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if (!wr_idx.found() || wr_idx != sccwr_idx)
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return;
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Instruction* wr_instr = ctx.get(wr_idx);
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if (!wr_instr->isSALU() || wr_instr->definitions.size() < 2 ||
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wr_instr->definitions[1].physReg() != scc)
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return;
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/* Look for instructions which set SCC := (D != 0) */
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switch (wr_instr->opcode) {
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case aco_opcode::s_bfe_i32:
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case aco_opcode::s_bfe_i64:
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case aco_opcode::s_bfe_u32:
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case aco_opcode::s_bfe_u64:
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case aco_opcode::s_and_b32:
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case aco_opcode::s_and_b64:
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case aco_opcode::s_andn2_b32:
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case aco_opcode::s_andn2_b64:
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case aco_opcode::s_or_b32:
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case aco_opcode::s_or_b64:
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case aco_opcode::s_orn2_b32:
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case aco_opcode::s_orn2_b64:
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case aco_opcode::s_xor_b32:
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case aco_opcode::s_xor_b64:
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case aco_opcode::s_not_b32:
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case aco_opcode::s_not_b64:
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case aco_opcode::s_nor_b32:
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case aco_opcode::s_nor_b64:
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case aco_opcode::s_xnor_b32:
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case aco_opcode::s_xnor_b64:
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case aco_opcode::s_nand_b32:
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case aco_opcode::s_nand_b64:
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case aco_opcode::s_lshl_b32:
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case aco_opcode::s_lshl_b64:
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case aco_opcode::s_lshr_b32:
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case aco_opcode::s_lshr_b64:
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case aco_opcode::s_ashr_i32:
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case aco_opcode::s_ashr_i64:
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case aco_opcode::s_abs_i32:
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case aco_opcode::s_absdiff_i32: break;
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default: return;
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}
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/* Use the SCC def from wr_instr */
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ctx.uses[instr->operands[0].tempId()]--;
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instr->operands[0] = Operand(wr_instr->definitions[1].getTemp(), scc);
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ctx.uses[instr->operands[0].tempId()]++;
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/* Set the opcode and operand to 32-bit */
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instr->operands[1] = Operand::zero();
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instr->opcode =
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(instr->opcode == aco_opcode::s_cmp_eq_u32 || instr->opcode == aco_opcode::s_cmp_eq_i32 ||
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instr->opcode == aco_opcode::s_cmp_eq_u64)
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? aco_opcode::s_cmp_eq_u32
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: aco_opcode::s_cmp_lg_u32;
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} else if ((instr->format == Format::PSEUDO_BRANCH && instr->operands.size() == 1 &&
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instr->operands[0].physReg() == scc) ||
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instr->opcode == aco_opcode::s_cselect_b32) {
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/* For cselect, operand 2 is the SCC condition */
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unsigned scc_op_idx = 0;
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if (instr->opcode == aco_opcode::s_cselect_b32) {
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scc_op_idx = 2;
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}
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Idx wr_idx = last_writer_idx(ctx, instr->operands[scc_op_idx]);
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if (!wr_idx.found())
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return;
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Instruction* wr_instr = ctx.get(wr_idx);
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/* Check if we found the pattern above. */
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if (wr_instr->opcode != aco_opcode::s_cmp_eq_u32 &&
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wr_instr->opcode != aco_opcode::s_cmp_lg_u32)
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return;
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if (wr_instr->operands[0].physReg() != scc)
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return;
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if (!wr_instr->operands[1].constantEquals(0))
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return;
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/* The optimization can be unsafe when there are other users. */
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if (ctx.uses[instr->operands[scc_op_idx].tempId()] > 1)
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return;
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if (wr_instr->opcode == aco_opcode::s_cmp_eq_u32) {
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/* Flip the meaning of the instruction to correctly use the SCC. */
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if (instr->format == Format::PSEUDO_BRANCH)
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instr->opcode = instr->opcode == aco_opcode::p_cbranch_z ? aco_opcode::p_cbranch_nz
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: aco_opcode::p_cbranch_z;
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else if (instr->opcode == aco_opcode::s_cselect_b32)
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std::swap(instr->operands[0], instr->operands[1]);
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else
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unreachable(
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"scc_nocompare optimization is only implemented for p_cbranch and s_cselect");
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}
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/* Use the SCC def from the original instruction, not the comparison */
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ctx.uses[instr->operands[scc_op_idx].tempId()]--;
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instr->operands[scc_op_idx] = wr_instr->operands[0];
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}
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}
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void
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try_combine_dpp(pr_opt_ctx& ctx, aco_ptr<Instruction>& instr)
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{
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/* We are looking for the following pattern:
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*
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* v_mov_dpp vA, vB, ... ; move instruction with DPP
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* v_xxx vC, vA, ... ; current instr that uses the result from the move
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*
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* If possible, the above is optimized into:
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*
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* v_xxx_dpp vC, vB, ... ; current instr modified to use DPP directly
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*
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*/
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if (!instr->isVALU() || instr->isDPP())
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return;
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for (unsigned i = 0; i < MIN2(2, instr->operands.size()); i++) {
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Idx op_instr_idx = last_writer_idx(ctx, instr->operands[i]);
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if (!op_instr_idx.found())
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continue;
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const Instruction* mov = ctx.get(op_instr_idx);
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if (mov->opcode != aco_opcode::v_mov_b32 || !mov->isDPP())
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continue;
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bool dpp8 = mov->isDPP8();
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if (!can_use_DPP(instr, false, dpp8))
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return;
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/* If we aren't going to remove the v_mov_b32, we have to ensure that it doesn't overwrite
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* it's own operand before we use it.
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*/
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if (mov->definitions[0].physReg() == mov->operands[0].physReg() &&
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(!mov->definitions[0].tempId() || ctx.uses[mov->definitions[0].tempId()] > 1))
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continue;
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/* Don't propagate DPP if the source register is overwritten since the move. */
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if (is_clobbered_since(ctx, mov->operands[0], op_instr_idx))
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continue;
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if (i && !can_swap_operands(instr, &instr->opcode))
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continue;
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if (!dpp8) /* anything else doesn't make sense in SSA */
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assert(mov->dpp16().row_mask == 0xf && mov->dpp16().bank_mask == 0xf);
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if (--ctx.uses[mov->definitions[0].tempId()])
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ctx.uses[mov->operands[0].tempId()]++;
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convert_to_DPP(instr, dpp8);
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if (dpp8) {
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DPP8_instruction* dpp = &instr->dpp8();
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if (i) {
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std::swap(dpp->operands[0], dpp->operands[1]);
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}
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dpp->operands[0] = mov->operands[0];
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memcpy(dpp->lane_sel, mov->dpp8().lane_sel, sizeof(dpp->lane_sel));
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} else {
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DPP16_instruction* dpp = &instr->dpp16();
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if (i) {
|
|
std::swap(dpp->operands[0], dpp->operands[1]);
|
|
std::swap(dpp->neg[0], dpp->neg[1]);
|
|
std::swap(dpp->abs[0], dpp->abs[1]);
|
|
}
|
|
dpp->operands[0] = mov->operands[0];
|
|
dpp->dpp_ctrl = mov->dpp16().dpp_ctrl;
|
|
dpp->bound_ctrl = true;
|
|
dpp->neg[0] ^= mov->dpp16().neg[0] && !dpp->abs[0];
|
|
dpp->abs[0] |= mov->dpp16().abs[0];
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
|
|
void
|
|
process_instruction(pr_opt_ctx& ctx, aco_ptr<Instruction>& instr)
|
|
{
|
|
try_apply_branch_vcc(ctx, instr);
|
|
|
|
try_optimize_scc_nocompare(ctx, instr);
|
|
|
|
try_combine_dpp(ctx, instr);
|
|
|
|
if (instr)
|
|
save_reg_writes(ctx, instr);
|
|
|
|
ctx.current_instr_idx++;
|
|
}
|
|
|
|
} // namespace
|
|
|
|
void
|
|
optimize_postRA(Program* program)
|
|
{
|
|
pr_opt_ctx ctx;
|
|
ctx.program = program;
|
|
ctx.uses = dead_code_analysis(program);
|
|
ctx.instr_idx_by_regs.resize(program->blocks.size());
|
|
|
|
/* Forward pass
|
|
* Goes through each instruction exactly once, and can transform
|
|
* instructions or adjust the use counts of temps.
|
|
*/
|
|
for (auto& block : program->blocks) {
|
|
ctx.reset_block(&block);
|
|
|
|
for (aco_ptr<Instruction>& instr : block.instructions)
|
|
process_instruction(ctx, instr);
|
|
}
|
|
|
|
/* Cleanup pass
|
|
* Gets rid of instructions which are manually deleted or
|
|
* no longer have any uses.
|
|
*/
|
|
for (auto& block : program->blocks) {
|
|
auto new_end = std::remove_if(block.instructions.begin(), block.instructions.end(),
|
|
[&ctx](const aco_ptr<Instruction>& instr)
|
|
{ return !instr || is_dead(ctx.uses, instr.get()); });
|
|
block.instructions.resize(new_end - block.instructions.begin());
|
|
}
|
|
}
|
|
|
|
} // namespace aco
|