Commit Graph

75428 Commits

Author SHA1 Message Date
Eric Anholt 02bcb443ee vc4: Warn instead of abort()ing on exec ioctl failures.
It's really harsh to abort() the X Server because of a momentary failure
(particularly -ENOMEM).  I don't see a way to pass an -ENOMEM up the stack
from here, but we can at least log to stderr before proceeding on.

Cc: "11.1" <mesa-stable@lists.freedesktop.org>
2015-12-15 12:02:44 -08:00
Andreas Boll a2140b0571 docs: Replace sourceforge logo with a text link
Fixes the following Lintian (Debian package checker) error:

privacy-breach-logo

  usr/share/doc/mesa-common-dev/contents.html
    (http://sourceforge.net/sflogo.php?group_id=3&amp;type=1)
  usr/share/doc/mesa-common-dev/thanks.html
    (http://sourceforge.net/sflogo.php?group_id=3&amp;type=1)

The extended description of this tag is:

    This package creates a potential privacy breach by fetching a logo
at runtime.

    Before using a local copy you should check that the logo is suitable
for main. You can get help with determining this by posting a link to
the logo and a copy of, or a link to, the logo copyright and license
information to the debian-legal mailing list.

    Please replace any scripts, images, or other remote resources with
non-remote resources. It is preferable to replace them with text and
links but local copies of the remote resources are also acceptable as
long as they don't also make calls to remote services. Please ensure
that the remote resources are suitable for Debian main before making
local copies of them.

    Severity: serious, Certainty: possible

    Check: files, Type: binary, udeb

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-12-15 17:57:25 +01:00
Nicolai Hähnle c8d9d289ff radeonsi: fix perfcounter selection for SI_PC_MULTI_BLOCK layouts
The incorrectly computed register count caused lockups.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-15 11:23:40 -05:00
Nicolai Hähnle 149d049676 gallium/radeon: remove unnecessary test in r600_pc_query_add_result
This test is a left-over of the initial development. It is unneeded and
misleading, so let's get rid of it.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-15 11:23:40 -05:00
Nicolai Hähnle 819543adb4 mesa/main: use BITSET_FOREACH_SET in perf_monitor_result_size
This should make the code both faster and slightly clearer.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2015-12-15 11:23:40 -05:00
Emil Velikov 9c0773958e docs: add news item and link release notes for 11.1.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2015-12-15 15:07:03 +00:00
Emil Velikov b8394ef3df docs: add sha256 checksums for 11.0.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 525f3c2c28cd083b37e1f6a27f503af1c4781141)
2015-12-15 15:07:02 +00:00
Emil Velikov 5497e119a5 docs: Update 11.1.0 release notes
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 5a616125acf0ac043d2d44b7a8e804739d55014e)
2015-12-15 15:07:02 +00:00
Rob Clark e677b3047b freedreno/a4xx: fix fragcoord.z + fragdepth
It seems like disabling earlyz on a4xx also, by defaults, disables
fragcoord.z to the FS.  For frag shaders that both read fragcoord(.z)
and write fragdepth, we need to set some extra bits to prevent a
lockup.

This lets us get rid of the hack of disabling fragcoord.z (which
prevented 0ad from lockups, but resulted in rendering corruption).  Also
fixes fbo-depth-sample-compare.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-12-15 09:40:54 -05:00
Rob Clark cad0920d11 freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-12-15 09:39:10 -05:00
Rob Clark 249b2be3bc freedreno/ir3/cmdline: don't dump nir by default
By default we only want the disasm dumped, which we get anyways.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-12-15 09:39:10 -05:00
Christian König 10b7a7c344 st/va: remove nonesense HEVC picture id handling
The picture id in this case is a VA-API surface handle, checking
for a certain value can't be correct.

Signed-off-by: Christian König <christian.koenig@amd.com>
2015-12-15 11:25:02 +01:00
Chris Forbes af5ca43f26 i965: Allocate URB space for HS and DS stages when required.
v2: (by Ken, incorporating feedback from Matt Turner):
- Rewrite the push constant allocation code to be clearer.
- Only apply the minimum VS entries workaround on Gen 8.

v3: (by Ken)
- Fix a bug in v2 where we failed to allocate the full push constant
  space when the number of enabled stages didn't divide the available
  push constant space evenly.  (Any left over space is now allocated
  to the PS, as it was in v1.)
- Fix an off-by-one error in v2's number of enabled stages calculation.
- Use DIV_ROUND_UP for nicer formatting.
- Line wrapping fixes.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-12-15 02:16:14 -08:00
Timothy Arceri 8c0963f9d3 docs: mark input/output block locations as DONE
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-15 13:10:51 +11:00
Timothy Arceri 0aeb9b3e5e glsl: add support for explicit locations inside interface blocks
This change also adds explicit location support for structs and interfaces which
is currently missing in Mesa but is allowed with SSO and GLSL 1.50+.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-15 13:10:44 +11:00
Timothy Arceri 183c606066 glsl: simplify interface matching
This makes the code easier to follow, should be more efficient
and will makes it easier to add matching via explicit locations
in the following patch.

This patch also replaces the hash table with the newer
resizable hash table this should be more suitable as the table
is likely to only contain a small number of entries.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-15 13:10:39 +11:00
Roland Scheidegger 8e264765a4 draw: remove clip_vertex from vertex header
vertex header had both clip_pos and clip_vertex.
We only really need one (clip_pos) because the draw llvm shader would
overwrite the position output from the vs with the viewport transformed.
However, we don't really need the second one, which was only really used
for gl_ClipVertex - if the shader didn't have that the values were just
duplicated to both clip_pos and clip_vertex. So, just use this from the vs
output instead when we actually need it.
Also change clip debug to output both the data from clip_pos and the
clipVertex output (if available).
Makes some things more complex, some things less complex, but seems more
easy to understand what clipping actually does (and what values it uses
to do its magic).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-15 02:03:40 +01:00
Roland Scheidegger 1775400a20 draw: use clip_pos, not clip_vertex for the fake guardband xy point clipping
Seems obvious now this should use the data from position and not clip_vertex
(albeit might not really make a difference).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-15 02:03:40 +01:00
Roland Scheidegger 8575ddb644 draw: rename vertex header members
clip -> clip_vertex and pre_clip_pos -> clip_pos.
Looks more obvious to me what these values actually represent (so use
something resembling the vs output names).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-15 02:03:40 +01:00
Roland Scheidegger 1b22815af6 draw: don't pretend have_clipdist is per-vertex
This is just for code cleanup, conceptually the have_clipdist really
isn't per-vertex state, so don't put it there (just dependent on the
shader). Even though there wasn't really any overhead associated with
this, we shouldn't store random shader information in the vertex header.

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-15 02:03:40 +01:00
Roland Scheidegger 9e3f2af3c3 draw: use position not clipVertex output for xyz view volume clipping
I'm pretty sure this should use position (i.e. pre_clip_pos) and not
the output from clipVertex. Albeit piglit doesn't care. It is what we
use in the clip test, and it is what every other driver does (as they
don't even have clipVertex output and lower the additional planes to
clip distances).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-15 02:03:40 +01:00
Kenneth Graunke 77cc2666b1 i965: Use DIV_ROUND_UP() in gen7_urb.c code.
This is a newer convention, which we prefer over ALIGN(x, n) / n.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-12-14 14:56:14 -08:00
Kenneth Graunke 9f0944d15b i965: Make TES inputs match TCS outputs.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:29 -08:00
Kenneth Graunke 4fac950010 i965: Force VS -> TCS varyings to use the SSO VUE map layout.
The compact VUE map only works when varying packing is in use.
Unfortunately, varying packing is disabled for TCS inputs.

This is needed to fix Piglit's tcs-input-read-array-interface test.

v2: Make lines fit in 80 columns (caught by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:18 -08:00
Kenneth Graunke bee42cc1f7 i965: Handle TCS outputs and TES inputs.
TCS outputs and TES inputs both refer to a common "patch URB entry"
shared across all invocations.  First, there are some number of
per-patch entries.  Then, there are per-vertex entries accessed via
an offset for the variable and a stride times the vertex index.

Because these calculations need to be done in both the vec4 and scalar
backends, it's simpler to just compute the offset calculations in NIR.
It doesn't necessarily make much sense to use per-vertex intrinsics
afterwards, but that at least means we don't lose the per-patch vs.
per-vertex information.

v2: Use is_input/is_output helpers (suggested by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:13 -08:00
Kenneth Graunke 31140d097a i965: Handle TCS inputs and TES outputs.
TES outputs work exactly like VS outputs, so we can simply add a case
statement for those.

TCS inputs are very similar to geometry shaders - they're arrays of
per-vertex data.  We use the same method I used for the scalar GS
backend.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:07 -08:00
Kenneth Graunke 1f46163acb i965: Add tessellation shader VUE map code.
Based on a patch by Chris Forbes, but largely rewritten by Ken.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:01 -08:00
Kenneth Graunke 9f3917bf37 i965: Fix partial variable access for geometry shaders in SSO mode.
Without varying packing, if a VS writes a compound variable, and the GS
only reads part of it, the base location of the variable may not
actually be in the VUE map.

To cope with this, we do lowering in terms of varying slots, add any
constant offsets to the base, and then do the VUE map remapping.  This
ensures we only look up VUE map entries for slots which actually exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-12-14 14:39:38 -08:00
Kenneth Graunke 8c4deb10df i965: Separate base offset/constant offset combining from remapping.
My tessellation branch has two additional remap functions.  I don't want
to replicate this logic there.

v2: Handle inputs/outputs separately (suggested by Jason Ekstrand).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-12-14 14:39:34 -08:00
Kenneth Graunke 106c3a8a48 nir: Fix number of indices on shared variable store intrinsics.
Shared variables and input reworks landed around the same time.
Presumably, this was some sort of mistake in rebase conflict resolution.

This really only affects the num_indices field in nir_intrinsic_infos,
which is rarely used.  However, it's used by the printer.

Found by inspection.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-12-14 14:27:38 -08:00
Ian Romanick 96dc732ed8 meta/generate_mipmap: Work-around GLES 1.x problem with GL_DRAW_FRAMEBUFFER
GL_DRAW_FRAMEBUFFER does not exist in OpenGL ES 1.x, and since
_mesa_meta_begin hasn't been called yet, we have to work-around API
difficulties.  The whole reason that GL_DRAW_FRAMEBUFFER is used instead
of GL_FRAMEBUFFER is that the read framebuffer may be different.  This
is moot in OpenGL ES 1.x.

I have another patch series that would also fix this (by removing the
calls to _mesa_BindFramebuffer and friends), but it's not quite ready
yet... and I think it may be a bit heavy for some stable branches.
Consider this a stop-gap fix.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93215
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2015-12-14 13:09:15 -08:00
Samuel Pitoiset 71135e275f nvc0: check return value of nvc0_program_validate()
Spotted by Coverity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-14 19:08:42 +01:00
Samuel Pitoiset 54f58210c2 nv50: check return value of nouveau_object_new()
When ret == 0, obj is not NULL. Spotted by Coverity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-14 19:08:39 +01:00
Samuel Pitoiset 3f7462b792 nv50,nvc0: make use of unreachable() when invalid texture target happens
Spotted by Coverity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-14 19:08:25 +01:00
Christian König 8b52fa71ac st/va: handle default post process regions
Avoid referencing NULL pointers.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>
2015-12-14 11:54:55 +01:00
Christian König f6dd31c1cf st/va: fix unused variable warning
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
2015-12-14 11:54:55 +01:00
Christian König 025d97381e st/va: clean up post process includes
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>
2015-12-14 11:54:54 +01:00
Christian König 27a276f625 st/va: cleanup filter color standard handling
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: ulien Isorce <j.isorce@samsung.com>
2015-12-14 11:54:54 +01:00
Tapani Pälli 8b79258cfe meta: clear_state structure cleanup
Remove unused variables from clear_state and use a hardcoded location
for color uniform to get rid of 2 more variables. Modify shaders to use
explicit location for vertex attribute too as extension is enabled.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-12-14 08:01:49 +02:00
Ilia Mirkin eca8f38dcf glsl: assign varying locations to tess shaders when doing SSO
GRID Autosport uses SSO shaders. When a tessellation evaluation shader
is passed through this, it triggers assertion failures down the line
with unassigned varying locations. Make sure to do this when the first
shader in the pipeline is not a vertex shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-13 11:35:28 -05:00
Neil Roberts 839793680f i965: Use MESA_FORMAT_B8G8R8X8_SRGB for RGB visuals
Previously if the visual didn't have an alpha channel then it would
pick a format that is not sRGB-capable. I don't think there's any
reason not to always have an sRGB-capable visual. Since 28090b30 there
are now visuals advertised without an alpha channel which means that
games that don't request alpha bits in the config would end up without
an sRGB-capable visual. This was breaking supertuxkart which assumes
the winsys buffer is always sRGB-capable.

The previous code always used an RGBA format if the visual config
itself was marked as sRGB-capable regardless of whether the visual has
alpha bits. I think we don't actually advertise any sRGB-capable
visuals (but we just use sRGB formats anyway) so it shouldn't make any
difference. However this patch also changes it to use RGBX if an
sRGB-capable visual is requested without alpha bits for consistency.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92759
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-13 14:29:42 +00:00
Neil Roberts 43f4be5f06 i965: Add B8G8R8X8_SRGB to the alpha format override
brw_init_surface_formats overrides the render format for RGBX formats
which aren't supported for rendering so that they internally use RGBA
instead. However, B8G8R8X8_SRGB was missing so it wasn't marked as a
renderable format. This patch just adds it.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-13 14:29:41 +00:00
Neil Roberts c769efda93 i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_format
This will be used in a subsequent patch as the format for RGB visuals.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-13 14:29:38 +00:00
Ilia Mirkin 7752bbc44e gk104/ir: simplify and fool-proof texbar algorithm
With the current algorithm, we only look at tex uses. However there's a
write-after-write hazard where we might decide to, on some path, not use
a texture's output at all, but instead to write a different value to
that register. However without the barrier, the texture might complete
later and overwrite that value.

This fixes Unreal Elemental demo on GK110/GK208, flightgear on GK10x,
and likely other random-looking failures.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
2015-12-12 18:10:16 -05:00
Ilia Mirkin d35695096d nv50/ir: combine sequences of conversions
In some cases shaders want non-default rounding when converting float to
integer. This can be done in one go, so merge the two ops. This comes up
in the packUnorm4x8 & co functions, as well as a few random shaders.
Overall shader-db impact is minimal, helping a handful of witcher2 and
other misc shaders.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:16 -05:00
Ilia Mirkin dbca0f3eba nv50/ir: manually optimize multiplication expansion logic
The conversion of 32-bit integer multiplies into 16-bit ones happens
after the regular optimization loop. However it's fairly common to
multiply by a small integer, rendering some of the expansion pointless.

Firstly, propagate immediates when possible into mul ops, secondly just
remove the ops when they are unnecessary.

Including the change to generate imad immediates, the effect is:

total instructions in shared programs : 6365463 -> 6351898 (-0.21%)
total gprs used in shared programs    : 728684 -> 728684 (0.00%)
total local used in shared programs   : 9904 -> 9904 (0.00%)
total bytes used in shared programs   : 44001576 -> 44036120 (0.08%)

                local        gpr       inst      bytes
    helped           0           0        3288           4
      hurt           0           0           0         842

It's easy for this to hurt bytes since we end up always generating the
8-byte form, while we can't always get rid of the immediate in question.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:16 -05:00
Ilia Mirkin 3af83c4bc7 nv50/ir: fix imul emission in the presence of an immediate
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:15 -05:00
Ilia Mirkin a0b5d5beed nv50/ir: teach post-ra immediate folding into mad about integers
There will usually be a split before the mad op, peer through that and
pick out the right word of the immediate.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:15 -05:00
Ilia Mirkin ab70ea1353 nv50/ir: add short imad support
Support emission of the short imad, but also include it in the various
logic that tries to make it possible to emit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:15 -05:00
Ilia Mirkin 6aca7fecb7 nv50/ir: can't have predication and immediates
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-12 18:10:15 -05:00