Commit Graph

114687 Commits

Author SHA1 Message Date
Kevin Strasser f4703f1c10 i965: Add handling for fp16 configs
Expose configs when allow_fp16_configs has been enabled and
DRI_LOADER_CAP_FP16 is set in the loader.

Also, define a new dri configuration option so users can disable exposure of
fp16 formats. Make fp16 opt-in for i965.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-08-21 18:36:57 +00:00
Kevin Strasser 4861d2a395 gbm: Add buffer handling and visuals for fp16 formats
Define and set a new loader cap DRI_LOADER_CAP_FP16, indicating that gbm can
handle fp16 formats.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-08-21 18:36:57 +00:00
Kevin Strasser a427c20080 dri: Add fp16 formats
Add dri formats for RGBA ordered 64 bpp IEEE 754 half precision floating
point. Leverage existing offscreen render support for
MESA_FORMAT_RGBA_FLOAT16 and MESA_FORMAT_RGBX_FLOAT16.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-08-21 18:36:57 +00:00
Kevin Strasser 482ed4347d egl: Handle dri configs with floating point pixel data
In the case that __DRI_ATTRIB_FLOAT_BIT is set in the dri config, set
EGL_COLOR_COMPONENT_TYPE_FLOAT_EXT in the egl config. Add a field to the
platform driver visual to indicate if it has components that are in floating
point form.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-08-21 18:36:57 +00:00
Kevin Strasser 86d31c2c12 dri: Handle configs with floating point pixel data
In order to handle pixel formats that consist of floating point data, enable
floatMode field in the dri config, and set __DRI_ATTRIB_FLOAT_BIT in the
render type attribute.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-08-21 18:36:57 +00:00
Kevin Strasser d4a9010338 glx: Add fields for color shifts
glx doesn't read the masks from the dri config directly, but for consistency
add shifts to the glxconfig.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-08-21 18:36:57 +00:00
Kevin Strasser 7b4ed2b513 egl: Convert configs to use shifts and sizes instead of masks
Change dri2_add_config to take arrays of shifts and sizes, and compare with
those set in the dri config. Convert all platform driver masks
to shifts and sizes.

In order to handle older drivers, where shift attributes aren't available,
we fall back to the mask attributes and compute the shifts with ffs.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-08-21 18:36:57 +00:00
Kevin Strasser 3562f48c9d util: move bitcount to bitscan.h
bitcount is free from the pipe header dependencies that make u_math.h hard
to include by non-gallium specific code, so move it to bitscan.h. bitscan.h
is included by u_math.h so existing references will continue working.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-08-21 18:36:57 +00:00
Kevin Strasser 5a747306ce dri: Add config attributes for color channel shift
The existing mask attributes can only support up to 32 bpp. Introduce
per-channel SHIFT attributes that indicate how many bits, from lsb towards
msb, the bit field is offset. A shift of -1 will indicate that there is no
bit field set for the channel.

As old loaders will still be looking for masks, we set the masks to 0 for
any formats wider than 32 bpp.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-08-21 18:36:57 +00:00
Kevin Strasser 9328e7c04c gallium: Use consistent approach for config format filtering
rgb10 uses an 'if(allowed) continue' approach, do the same for rgba_ordering.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-08-21 18:36:57 +00:00
Kevin Strasser 4fb71604b7 i965: Add helper function for allowed config formats
The driver checks dri config options and loader caps to filter out certain
formats during config creation. Fold 4 call sites under a single helper
function.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-08-21 18:36:57 +00:00
Kevin Strasser d07a56dbc0 drm-uapi: Update headers for fp16 formats
From drm-next commit 88ab9c76d191ad8645b483f31e2b394b0f3e280e

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-08-21 18:36:57 +00:00
Andres Rodriguez bd960390bb radv: add RADV_DEBUG=allentrypoints
This debug option allows vkGet[Instance/Device]ProcAddr() to succeed
even if the extension associated with the requested entrypoint was not
enabled.

This has come in handy in a few instances when debugging VR
applications, so I thought it would be good to have a cleaned up version
upstreamed.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-08-21 17:47:35 +00:00
Alyssa Rosenzweig 0ae72df013 panfrost: Fix PIPE_BUFFER spacing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:44:45 -07:00
Alyssa Rosenzweig d4542f8cb5 panfrost: Implement depth range clipping
This should fix glDepthRangef issues. Eventually, something similar
should allow implementing the depth bounds test.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:44:45 -07:00
Alyssa Rosenzweig 5e268a01d2 panfrost: Don't bail on PIPE_BUFFER
We can handle some of it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:43:02 -07:00
Alyssa Rosenzweig 7f14916372 pan/midgard: Identify and disassemble indirect texture/sampler
A pair of special flags can turn the texture/sampler handle fields into
register selects. This means code like:

   texture(uTextures[hr28.w], ...)

can be compiled to something like:

   texture ..., fsampler[hr28.w], texture[hr28.w]

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:41:15 -07:00
Alyssa Rosenzweig 8c1bc3c000 pan/midgard: Breakout texture reg select printer
This data structure is shared in other parts of the texture word, so
let's streamline printing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:41:15 -07:00
Alyssa Rosenzweig aa404120e1 panfrost: Pass stream_output_info by reference
It's a large structure, apparently.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig 27b6264630 panfrost: Guard against NULL rasterizer explicitly
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig 5ebdd10eaf pan/bifrost: Correct file size signedness
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig 87afc2e2da panfrost: Fix missing ret assignment in DRM code
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig c43fa6b320 panfrost: Hoist bo != NULL check before dereference
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig a3c1ab2e9a panfrost: Hoist job != NULL check
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig 9cee21f0c9 panfrost: Prevent potential integer overflow in instancing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig 5bdc9096b7 panfrost: Clarify intention with PIPE_SWIZZLE_X check
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig 8fba6ab03d panfrost: Pay attention to framebuffer dimension sign
These are unsigned so the clamp-positive is redundant.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig 14a2032f0f pan/midgard: Mark fallthrough explicitly
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig ed58fd63b4 panfrost: Don't check reads_point_coord
Useless check.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig d0b9f094fd pan/midgard: Simplify contradictory check.
Coverity.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig 91a5b2657d pan/midgard: Reorder bits check to fix 8-bit masks
Coverity.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig 6189274f57 pan/midgard: Represent unused nodes by ~0
This allows nodes to be unsigned and prevents a class of weird
signedness bugs identified by Coverity.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig cda0ec67e6 pan/bifrost: Avoid buffer overflow in disassembler
This path shouldn't be possible for in-spec shaders, but let's be
defensive. (Because security, right? Mostly because Coverity.)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig 9ce45ac808 pan/decode: Remove all_zero
The checks confuse Coverity, so let's make it explicit what's going on.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:31 -07:00
Alyssa Rosenzweig 1060c48d46 pan/decode: Don't leak FBD pointer
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:30 -07:00
Alyssa Rosenzweig 52ac7dc5d0 pan/midgard: Allocate `dependencies` on stack
It's small; this way we don't leak memory.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:30 -07:00
Alyssa Rosenzweig bf036e127f pan/midgard: Free liveness info
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 10:38:30 -07:00
Jason Ekstrand c9a4793de8 v3d: Use the correct opcodes for signed image min/max
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-21 17:19:55 +00:00
Jason Ekstrand 021fa28163 intel/nir: Add a helper for getting BRW_AOP from an intrinsic
So many duplicated switch statements....

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-21 17:19:55 +00:00
Jason Ekstrand 951cf94521 nir: Add explicit signs to image min/max intrinsics
This better matches all the other atomic intrinsics such as those for
SSBOs and shared variables where the sign is part of the intrinsic
opcode.  Both generators (GLSL and SPIR-V) know the sign from the type
of the image variable or handle.  In SPIR-V, signed min/max are separate
opcodes from unsigned.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-21 17:19:55 +00:00
Alyssa Rosenzweig fc69a5cf73 pan/decode: Cleanup mali_attr printing
We can smush this into one-line per record as per usual. We still need
more validation and cleaning this up, especially around instancing. But
for LINEAR records, it works okay already.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 08:40:56 -07:00
Alyssa Rosenzweig 62e6673908 pan/decode: Validate attribute/varying buffer pointer
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 08:40:55 -07:00
Alyssa Rosenzweig be5e30c46b pan/decode: Include address in union mali_attr
No need to break it out into extra lines.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 08:40:55 -07:00
Alyssa Rosenzweig 68b9030db7 pan/decode: Use concise texture printing
This consolidates texture format and dimensionality into something simple:

    tiled rgba8_unorm.rgb1: 512x512

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 08:40:55 -07:00
Alyssa Rosenzweig 9f15f4d8e9 panfrost: Break up usage2 field
This is another bit field describing layout.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 08:40:55 -07:00
Alyssa Rosenzweig 9b203950ec pan/decode: Pretty-print sRGB format
We can just stick an "s" in if it's sRGB.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 08:40:55 -07:00
Alyssa Rosenzweig 47af32b15e panfrost: Remove ancient TODO
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 08:40:55 -07:00
Alyssa Rosenzweig 96f6b8a707 panfrost: nr_mipmap_levels -> levels
No need to be so verbose.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 08:40:55 -07:00
Alyssa Rosenzweig 024f9cf24f pan/decode: Validate texture dimensionality
Textures of a smaller dimension don't need higher dimensions printed.
This allows us to be more compact, while enforcing verification that
higher dimensions must be zero.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 08:40:55 -07:00
Alyssa Rosenzweig 8fc4ca82e3 pan/decode: Break out pandecode_texture function
It's massive and hugely nested indentation -- break it out so it's
legible.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-21 08:40:55 -07:00