Commit Graph

6947 Commits

Author SHA1 Message Date
Eric Engestrom f1eae2f8bb python: drop python2 support
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3674>
2021-08-14 21:44:32 +00:00
Lionel Landwerlin 19b7bbba73 anv/android: handle image bindings from gralloc buffers
When creating an image out of a swapchain on Android, the android
layer call will detect a VkBindImageMemorySwapchainInfoKHR in the
pNext chain of the vkBindImageMemory2() call and add a
VkNativeBufferANDROID in the chain. This is what we should use as
backing memory for that image.

v2: Fix a couple of obvious mistakes (Tapani)

v3: Silence build warning (Lionel)
    Fix invalid object argument to vk_error() (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: bc3c71b87a ("anv: don't try to access Android swapchains")
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5180
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12244>
2021-08-13 08:30:25 +00:00
Jason Ekstrand b8e2214ee5 anv: Use I915_USERPTR_PROBE when available
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12044>
2021-08-12 15:07:23 -05:00
Jason Ekstrand 512fa2f4da anv: Use I915_MMAP_OFFSET_FIXED for LMEM platforms
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11888>
2021-08-12 19:29:59 +00:00
Jason Ekstrand f3aabe068c anv/android: Drop unused device variables
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12308>
2021-08-11 23:57:52 +00:00
Jason Ekstrand 16a9cf6915 anv/android: Pass the correct pointer type to vk_errorf
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12308>
2021-08-11 23:57:52 +00:00
Jason Ekstrand 279fe1ae6d intel/perf: Use a char array for OA perf query data
drm_i915_query_perf_config::data is an unsized array and declaring a
struct containing an unsized array that isn't at the end is a GNU
extension which trips up Android builds.  Instead, stuff both into a
char array of the appropriate size.  This emulates what you'd normally
do to allocate one of these with malloc only on the stack.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12308>
2021-08-11 23:57:52 +00:00
Jason Ekstrand c858d30833 intel/vec4: Don't override emit_urb_write_opcode for SNB GS
The gfx6_gs_visitor overrides emit_urb_write_opcode but with a different
function signature.  This causes warnings with -Woverloaded-virtual.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12308>
2021-08-11 23:57:52 +00:00
Jason Ekstrand ce1a66fe3e meson/intel: Don't build genxml tests on Android
They require expat which we don't have on Android.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12308>
2021-08-11 23:57:52 +00:00
Dave Airlie 8a81d14271 intel/vec4: sel.cond writes the flags on Gfx4 and Gfx5
This is the equivalent of idr's
intel/fs: sel.cond writes the flags on Gfx4 and Gfx5

except for the vec4 backend.

This fixes buggy rendering seen with crocus on a qt trace.

v2 (idr): Trivial whitespace change.  Add unit tests.

v3: Fix type in comment in unit tests.  Noticed by Jason and Priit.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

Iron Lake
total instructions in shared programs: 8183077 -> 8184543 (0.02%)
instructions in affected programs: 198990 -> 200456 (0.74%)
helped: 0
HURT: 1355
HURT stats (abs)   min: 1 max: 8 x̄: 1.08 x̃: 1
HURT stats (rel)   min: 0.29% max: 6.00% x̄: 0.99% x̃: 0.70%
95% mean confidence interval for instructions value: 1.04 1.12
95% mean confidence interval for instructions %-change: 0.96% 1.03%
Instructions are HURT.

total cycles in shared programs: 238967672 -> 238962784 (<.01%)
cycles in affected programs: 4666014 -> 4661126 (-0.10%)
helped: 406
HURT: 314
helped stats (abs) min: 4 max: 54 x̄: 22.46 x̃: 18
helped stats (rel) min: <.01% max: 12.80% x̄: 1.82% x̃: 0.65%
HURT stats (abs)   min: 2 max: 112 x̄: 13.48 x̃: 12
HURT stats (rel)   min: <.01% max: 7.82% x̄: 0.81% x̃: 0.16%
95% mean confidence interval for cycles value: -8.60 -4.98
95% mean confidence interval for cycles %-change: -0.87% -0.49%
Cycles are helped.

GM45
total instructions in shared programs: 4986888 -> 4988354 (0.03%)
instructions in affected programs: 198990 -> 200456 (0.74%)
helped: 0
HURT: 1355
HURT stats (abs)   min: 1 max: 8 x̄: 1.08 x̃: 1
HURT stats (rel)   min: 0.29% max: 6.00% x̄: 0.99% x̃: 0.70%
95% mean confidence interval for instructions value: 1.04 1.12
95% mean confidence interval for instructions %-change: 0.96% 1.03%
Instructions are HURT.

total cycles in shared programs: 153577826 -> 153572938 (<.01%)
cycles in affected programs: 4666014 -> 4661126 (-0.10%)
helped: 406
HURT: 314
helped stats (abs) min: 4 max: 54 x̄: 22.46 x̃: 18
helped stats (rel) min: <.01% max: 12.80% x̄: 1.82% x̃: 0.65%
HURT stats (abs)   min: 2 max: 112 x̄: 13.48 x̃: 12
HURT stats (rel)   min: <.01% max: 7.82% x̄: 0.81% x̃: 0.16%
95% mean confidence interval for cycles value: -8.60 -4.98
95% mean confidence interval for cycles %-change: -0.87% -0.49%
Cycles are helped.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12191>
2021-08-11 13:09:32 -07:00
Ian Romanick 38807ceeae intel/fs: sel.cond writes the flags on Gfx4 and Gfx5
On Gfx4 and Gfx5, sel.l (for min) and sel.ge (for max) are implemented
using a separte cmpn and sel instruction.  This lowering occurs in
fs_vistor::lower_minmax which is called very, very late... a long, long
time after the first calls to opt_cmod_propagation.  As a result,
conditional modifiers can be incorrectly propagated across sel.cond on
those platforms.

No tests were affected by this change, and I find that quite shocking.
After just changing flags_written(), all of the atan tests started
failing on ILK.  That required the change in cmod_propagatin (and the
addition of the prop_across_into_sel_gfx5 unit test).

Shader-db results for ILK and GM45 are below.  I looked at a couple
before and after shaders... and every case that I looked at had
experienced incorrect cmod propagation.  This affected a LOT of apps!
Euro Truck Simulator 2, The Talos Principle, Serious Sam 3, Sanctum 2,
Gang Beasts, and on and on... :(

I discovered this bug while working on a couple new optimization
passes.  One of the passes attempts to remove condition modifiers that
are never used.  The pass made no progress except on ILK and GM45.
After investigating a couple of the affected shaders, I noticed that
the code in those shaders looked wrong... investigation led to this
cause.

v2: Trivial changes in the unit tests.

v3: Fix type in comment in unit tests.  Noticed by Jason and Priit.

v4: Tweak handling of BRW_OPCODE_SEL special case.  Suggested by Jason.

Fixes: df1aec763e ("i965/fs: Define methods to calculate the flag subset read or written by an fs_inst.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Dave Airlie <airlied@redhat.com>

Iron Lake
total instructions in shared programs: 8180493 -> 8181781 (0.02%)
instructions in affected programs: 541796 -> 543084 (0.24%)
helped: 28
HURT: 1158
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.35% max: 0.86% x̄: 0.53% x̃: 0.50%
HURT stats (abs)   min: 1 max: 3 x̄: 1.14 x̃: 1
HURT stats (rel)   min: 0.12% max: 4.00% x̄: 0.37% x̃: 0.23%
95% mean confidence interval for instructions value: 1.06 1.11
95% mean confidence interval for instructions %-change: 0.31% 0.38%
Instructions are HURT.

total cycles in shared programs: 239420470 -> 239421690 (<.01%)
cycles in affected programs: 2925992 -> 2927212 (0.04%)
helped: 49
HURT: 157
helped stats (abs) min: 2 max: 284 x̄: 62.69 x̃: 70
helped stats (rel) min: 0.04% max: 6.20% x̄: 1.68% x̃: 1.96%
HURT stats (abs)   min: 2 max: 48 x̄: 27.34 x̃: 24
HURT stats (rel)   min: 0.02% max: 2.91% x̄: 0.31% x̃: 0.20%
95% mean confidence interval for cycles value: -0.80 12.64
95% mean confidence interval for cycles %-change: -0.31% <.01%
Inconclusive result (value mean confidence interval includes 0).

GM45
total instructions in shared programs: 4985517 -> 4986207 (0.01%)
instructions in affected programs: 306935 -> 307625 (0.22%)
helped: 14
HURT: 625
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.35% max: 0.82% x̄: 0.52% x̃: 0.49%
HURT stats (abs)   min: 1 max: 3 x̄: 1.13 x̃: 1
HURT stats (rel)   min: 0.12% max: 3.90% x̄: 0.34% x̃: 0.22%
95% mean confidence interval for instructions value: 1.04 1.12
95% mean confidence interval for instructions %-change: 0.29% 0.36%
Instructions are HURT.

total cycles in shared programs: 153827268 -> 153828052 (<.01%)
cycles in affected programs: 1669290 -> 1670074 (0.05%)
helped: 24
HURT: 84
helped stats (abs) min: 2 max: 232 x̄: 64.33 x̃: 67
helped stats (rel) min: 0.04% max: 4.62% x̄: 1.60% x̃: 1.94%
HURT stats (abs)   min: 2 max: 48 x̄: 27.71 x̃: 24
HURT stats (rel)   min: 0.02% max: 2.66% x̄: 0.34% x̃: 0.14%
95% mean confidence interval for cycles value: -1.94 16.46
95% mean confidence interval for cycles %-change: -0.29% 0.11%
Inconclusive result (value mean confidence interval includes 0).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12191>
2021-08-11 13:09:20 -07:00
Marcin Ślusarz 7810ca596c intel/compiler: use nir_shader_instructions_pass in brw_nir_apply_attribute_workarounds
Changes:
- removal of attr_wa_state (it's passed directly)
- nir_metadata_preserve(..., nir_metadata_all) is called when pass doesn't
  make progress

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12324>
2021-08-11 11:23:30 +00:00
Tapani Pälli ff669ea93b anv/android: fix build error due refactoring
Fixes: e08370dc37 ("anv: disable aux for exportable images without modifiers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5208
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12300>
2021-08-11 04:54:05 +00:00
Jason Ekstrand 11ac7d9e02 intel/eu: Set scope to TILE for TGM flushes
Setting it to GPU can cause an L3$ flush in certain cases.  That's not
what we want as we really only care about coherency within the GPU.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12291>
2021-08-10 14:00:19 +00:00
Jason Ekstrand 56fe30cbfc anv: Make anv_image_aspect_to_plane take an anv_image*
It's called anv_image_* so it really should take an anv_image.  For the
couple of cases where we really want to pass in a set of aspects, we
leave an anv_aspect_to_plane() helper.  anv_image_aspect_to_plane() is
then just a wrapper around it which grabs the aspects from the image.

While we're in the area, sprinkle some const around.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand e37c2d923a anv: Rework our aspect/plane helpers
The new versions should have identical output, just a simpler (and
probably faster) implementation and more/better asserts.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand 0a93c0364c anv/image: Rework YCbCr image aspects
The Vulkan 1.2.184 spec says:

    "When creating a VkImageView, if sampler Y′CBCR conversion is
    enabled in the sampler, the aspectMask of a subresourceRange used by
    the VkImageView must be VK_IMAGE_ASPECT_COLOR_BIT.

    When creating a VkImageView, if sampler Y′CBCR conversion is not
    enabled in the sampler and the image format is multi-planar, the
    image must have been created with
    VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT, and the aspectMask of the
    VkImageView’s subresourceRange must be VK_IMAGE_ASPECT_PLANE_0_BIT,
    VK_IMAGE_ASPECT_PLANE_1_BIT or VK_IMAGE_ASPECT_PLANE_2_BIT."

Previously, for YCbCr images, we were flipping this around.  For single-
plane views where VK_IMAGE_ASPECT_PLANE_N_BIT would be passed in by the
app, we would store VK_IMAGE_ASPECT_COLOR_BIT.  For multi-plane views
where the client says VK_IMAGE_ASPECT_COLOR_BIT, we would store a all of
the planes.  (There was also an extra bit of remapping that would
compact the planes in the non-existent case of a format with a non-
contiguous set of planes.)  The idea behind this was that for things
like rendering or single-plane sampling, storage, or compute, we want it
to look as much like a single-plane image as possible but we wanted the
multi-plane case to be the awkward one.

This commit changes it around so that iview->aspects is always exactly
the subset of image->vk.aspects represented by the view.  This is
identical to how aspects work for depth/stencil so it gains us some
consistency.

This commit also changes anv_image_view::aspect_mask to aspects to force
a full audit of the field.  As can be seen, there are only a few uses of
this field and they're all mostly fine:

 - A bunch of them are used to check for depth/stencil.  That hasn't
   changed.

 - Most of the checks for color already used ANY_COLOR_BIT, only one
   needed fixing.

 - There's a check that both src/depth are color for MSAA resolves.
   However, we don't support MSAA on YCbCr so there's no point in
   checking for ANY_COLOR_BIT.

There is a hidden usage of planes in anv_descriptor_set_write_image_view
that's not as obvious.  However, this function simply looks at
anv_image_view::n_planes and blindly fills out the descriptor
accordingly.  As long as image views with a single plane continue to
claim n_planes == 1, this will be fine.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand 32157f9059 anv: Stop assuming planes are in aspect-bit-order
Previously, we initialized vplane in anv_CreateImageView to 0 and
incremented it every iteration of the aspect loop.  This only works
because planes are guaranteed to be in aspect-bit-order which wasn't
documented anywhere.  Instead, drop this assumption and burn a couple
CPU cycles properly calculating vplane.

While we're here, make iplane const as well.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand 7e8fe42816 anv: Use anv_get_format_plane for color image view setup
When creating a single-plane view of a multi-plane image, we were
relying on vplane_aspect to be VK_IMAGE_ASPECT_COLOR_BIT so that
anv_get_format_plane of the single-plane view format would work.
Instead of relying on this quirk, we can drop vplane_aspect and rely
entirely on vplane to only be 0 in this case.  In the case of depth or
stencil images, we still need to grab the format aspect but we can use
the actual aspect and don't need the vplane_aspect trickery.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand 61807505e8 anv: Use anv_get_format_plane in anv_get_image_format_features
Once we get past depth/stencil, what we really want is plane 0 not the
color aspect.  A bunch of those formats don't have a single color
aspect.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand 4df2078e72 anv: Add a get_format_plane helper and use it in image setup
Unlike anv_get_format_aspect, this takes a plane number which is
relative to the set of aspects on the format.  There are a number of
cases where we already have the plane and so re-fetching it is useless.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand dc6794ec24 anv: Rework depth/stencil early return in anv_get_format_plane
The comment about modifiers is bogus because we check the modifier
before this check and return early.  Also, there's no reason why we need
to check the requested aspect when we could check the format itself.
anv_image_aspect_to_plane will ensure that the requested aspect is one
that actually exists.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand 4518ae8284 anv: Rename anv_get_format_plane to anv_get_format_aspect
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand 5dd55b0881 anv/blorp: Use the isl_surf for computing level_width/height in anv_image_ccs_op
Don't manually monkey around with the denominator scales.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand 9a267be039 anv/blorp: Drop some can_ycbcr checks
Vulkan allows us to, in theory, support ycbcr on single-plane formats if
the client really wants it.  Also, these functions should work on a
multi-plane color image as long as the client specifies the right
aspect.  This gets rid of our usage of can_ycbcr outside of anv_image.c.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Tapani Pälli 5e80cdbf8e anv: allow stencil memory export
This commit reverts 58e9371141 as now iris driver can import stencil.
This makes ext_external_objects-vk-stencil-display pass and X-Plane 11
vulkan rendering backend to work with anv + iris.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>
2021-08-09 05:38:50 +03:00
Tapani Pälli e08370dc37 anv: disable aux for exportable images without modifiers
This makes import easier on different gfx generations and we don't
have to lock down on a certain aux layout just yet.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>
2021-08-09 05:38:50 +03:00
Lionel Landwerlin bc3c71b87a anv: don't try to access Android swapchains
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5180
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12217>
2021-08-05 18:15:52 +00:00
Ian Romanick 9dfe7fbc6b isl: Use CLAMP macro instead of MIN of MAX
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12177>
2021-08-03 12:55:11 -07:00
Ian Romanick 72259a870f util: Add and use functions to calculate min and max int for a size
Many places need to know the maximum or minimum possible value for a
given size integer... so everyone just open-codes their favorite
version.  There is some potential to hit either undefined or
implementation-defined behavior, so having one version that Just Works
seems beneficial.

v2: Fix copy-and-pasted bug (INT64_MAX instead of INT64_MIN) in
u_intmin.  Noticed by CI.  Lol.  Rename functions
`s/u_(uint|int)(min|max)/u_\1N_\2/g`.  Suggested by Jason.  Add some
unit tests that would have caught the copy-and-paste bug before wasting
CI time.  Change the implementation of u_intN_min to use the same
pattern as stdint.h.  This avoids the integer division.  Noticed by
Jason.

v3: Add changes to convert_clear_color
(src/gallium/drivers/iris/iris_clear.c).  Suggested by Nanley.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12177>
2021-08-03 12:55:02 -07:00
Lionel Landwerlin 97be8e42e4 intel/disasm: fix missing oword index decoding
Also switch to array of strings to show high/low dwords.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: daba2894ff ("intel/disasm: decode/describe more send messages")
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12183>
2021-08-03 17:26:37 +00:00
Timothy Arceri a9ed4538ab nir: add indirect loop unrolling to compiler options
This is where it should be rather than having to pass it into the
optimisation pass every time.

It also allows us to call the loop analysis pass without having to
duplicate these options which we will do later in this series.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12064>
2021-08-03 10:54:50 +00:00
Timothy Arceri a654e39f15 intel/compiler: make sure swizzle is applied to if condition
This fixes a hang in the following piglit test when GCM moves a
UBO load outside of the loop.

tests/shaders/ssa/fs-if-def-else-break.shader_test

The end NIR ends up looking like this:

	vec2 32 ssa_3 = intrinsic load_ubo (ssa_2, ssa_0) (0, 1073741824, 0, 0, 8)
	vec1 32 ssa_4 = mov ssa_3.x
	vec1 32 ssa_5 = inot ssa_3.y
	/* succs: block_1 */
	loop {
           ...
           if ssa_5 { }
        }

Fixes: 1edf67fc3f ("intel/fs: Generate if instructions with inverted conditions")

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12064>
2021-08-03 10:54:50 +00:00
Rob Clark 6edf0d8e90 driconfig: Add support for device specific config
Add support for driconf overrides on a per-device level, for cases
where we don't want to override behavior for all devices supported
by a particular driver.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12135>
2021-08-02 16:37:24 -07:00
Dave Airlie de625dddee intel/genxml: fix raster operation field in blt genxml
This field should be a uint, further changes on top of previous
ones in this area

Fixes: 4d80ec8fcf ("intel/genxml: fix raster op fields on gen4/5")
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12164>
2021-08-03 05:38:25 +10:00
Sagar Ghuge 5ed5d08141 genxml/gen125: Update debug register fields according to HW
Updating fields helps to decode the error state correctly.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12133>
2021-08-02 16:45:31 +00:00
Sagar Ghuge 910d5f1973 genxml/gen12: Update debug register fields according to HW
Updating fields helps to decode the error state correctly.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12133>
2021-08-02 16:45:31 +00:00
Ian Romanick 5ffbee84a4 intel/compiler: Add id parameter to shader_perf_log callback
There are two problems with the current architecture.

In OpenGL, the id is supposed to be a unique identifier for a particular
log source.  This is done so that applications can (theoretically)
filter particular log messages.  The debug callback infrastructure in
Mesa assigns a uniqe value when a value of 0 is passed in.  This causes
the id to get set once to a unique value for each message.

By passing a stack variable that is initialized to 0 on every call,
every time the same message is logged, it will have a different id.
This isn't great, but it's also not catastrophic.

When threaded shader compiles are used, the id *pointer* is saved and
dereferenced at a possibly much later time on a possibly different
thread.  This causes one thread to access the stack from a different
thread... and that stack frame might not be valid any more. :(

I have not observed any crashes related to this particular issue.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12136>
2021-08-01 23:58:08 +00:00
Ian Romanick 043c5bf966 intel/compiler: Add id parameter to shader_debug_log callback
There are two problems with the current architecture.

In OpenGL, the id is supposed to be a unique identifier for a particular
log source.  This is done so that applications can (theoretically)
filter particular log messages.  The debug callback infrastructure in
Mesa assigns a uniqe value when a value of 0 is passed in.  This causes
the id to get set once to a unique value for each message.

By passing a stack variable that is initialized to 0 on every call,
every time the same message is logged, it will have a different id.
This isn't great, but it's also not catastrophic.

When threaded shader compiles are used, the id *pointer* is saved and
dereferenced at a possibly much later time on a possibly different
thread.  This causes one thread to access the stack from a different
thread... and that stack frame might not be valid any more. :(

This fixes shader-db crashes of various kinds on Iris with threaded
shader compiles enabled.

Fixes: 42c34e1ac8 ("iris: Enable threaded shader compilation")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12136>
2021-08-01 23:58:08 +00:00
Dave Airlie e79a78a16f intel/decode: add gfx4 vertex shader decode
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12160>
2021-08-02 07:23:58 +10:00
Dave Airlie 0dec873f2a intel/decode: add gfx4 constant buffer decode
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12160>
2021-08-02 07:23:38 +10:00
Dave Airlie c8783001c7 intel/fs: restrict max push length on older GPUs to a smaller amount
Fixes crash in dEQP-GLES2.functional.uniform_api.random.79

Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12093>
2021-07-30 15:17:21 +10:00
Iván Briano df338fe7d1 anv: Don't copy the lineStipple values if lineStipple is not enabled
If the passed VkPipelineRasterizationLineStateCreateInfoEXT wasn't zero
initialized, we copy garbage values that are later on used to set the
state and may end up crashing when they are beyond the limits of the HW.

v2 (Lionel): Simplify if condition

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12121>
2021-07-29 23:10:12 +00:00
Lionel Landwerlin b8e29e8936 anv: fix submission batching with perf queries
If we have 2 command buffers back to back, one with a query pool, one
without, we don't want to retain the second query pool value (NULL).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0a7224f3ff ("anv: group as many command buffers into a single execbuf")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12107>
2021-07-29 13:53:14 +00:00
Alejandro Piñeiro 476dc3c050 vulkan: add vk_spec_info_to_nir_spirv util method
All vulkan drivers have been copying anv's code to convert
VkSpecializationInfo into nir_spirv_specialization.

Recently there was a Vulkan spec change on allowed values for
VkSpecializationInfo, and all drivers got affected.

This commits creates a new helper, and uses it on all Vulkan Mesa
drivers.

v2: use (uint8_t*) castings, instead of void*, to avoid C2036 with
    MSVC (detected by the CI, inspired on what radv was doing)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12047>
2021-07-29 03:28:52 +00:00
Jason Ekstrand 49908c602f anv/android: Rework our handling of AHardwareBuffer imports
The current code we have for this is a bit of a mess, likely due to
trying too hard to put it in anv_android.c.  The external_format bit in
anv_image, for instance, really means "quit creation early" which is
something we want to do for AHardwareBuffer imports regardless of
whether or not they use a native format.  It gets set both by declaring
an AHardwareBuffer external handle type and by VkExternalFormatANDROID.
However, VkExternalFormatANDROID is only allowed for AHardwareBuffer
imports.  If we ever did get an external format outside the context of
an AHardwareBuffer import, we would end up with a useless partially
created image.

When we detect an AHardwareBuffer import, we punt off to a function in
anv_android.c that does nothing interesting but call anv_create_image
with AUX disabled and external_format = true.  The aux disable here is
useless because the actual isl_surf layout is done by resolve_ahw_image
which also sets ISL_SURF_USAGE_DISABLE_AUX_BIT.  As far as external
formats go, anv_image_from_external() sets it regardless of whether or
not there is actually an external format.

This commit replaces anv_image::external_format with anv_image::from_ahb
which is the thing we actually want to track for this.  We delete
anv_image_from_external and a bunch of the external_format handling
because it's all useless.  The end result is massively simpler and,
while it appears to blur the boundary between Android code and the rest
of the driver, it makes the whole flow more obvious.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12040>
2021-07-27 14:45:28 +00:00
Lionel Landwerlin 8a99873712 isl: fix mapping of format->stringname
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ed6e586562 ("intel: properly constify isl_format_layouts")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5110
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12051>
2021-07-26 07:16:28 +00:00
Jason Ekstrand 74ec2b12be nir/lower_tex: Rework invalid implicit LOD lowering
Only fragment and some compute shaders support implicit derivatives.
They're totally meaningless without helper invocations and some
understanding of the dispatch pattern.  We've got code to lower
nir_texop_tex in these shader stages to use an explicit derivative of 0
but it was pretty badly broken:

 1. It only handled nir_texop_tex, not nir_texop_txb or nir_texop_lod.

 2. It didn't take min_lod into account

 3. It was conflated with adding a missing LOD parameter to opcodes
    which expect one such as nir_texop_txf.  While not really a bug,
    this does make it way harder to reason about the code.

 4. Unless you set a flag (which most drivers don't), it left the
    opcode nir_texop_tex instead of nir_texop_txl which it should have
    been.

This reworks it to go through roughly the same path as other LOD
lowering only with a constant lod of 0 instead of calling out to
nir_texop_lod.  We also get rid of the lower_tex_without_implicit_lod
flag because most drivers set it and those that don't are probably
subtly broken.  If someone really wants to get nir_texop_tex in their
vertex shaders, they can write a new patch to add the flag back in.

Fixes: e382890e25 "nir: set default lod to texture opcodes that..."
Fixes: d5ac5d6e83 "nir: Add option to lower tex to txl when..."
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
2021-07-23 15:53:57 +00:00
Jason Ekstrand 7ecfbaf7f0 intel/blorp: Use nir_texop_txl
We set an explicit LOD immediately afterwards so we don't want implicit
mipmap selection.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
2021-07-23 15:53:57 +00:00
Jason Ekstrand 4465ca296d nir: Suffix all the MCS texture stuff _intel
It's intel-specific, used to get at MSAA compression information.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
2021-07-23 15:53:57 +00:00