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nir: Suffix all the MCS texture stuff _intel 

It's intel-specific, used to get at MSAA compression information.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
This commit is contained in:
Jason Ekstrand 2021-07-07 17:06:46 -05:00 committed by Marge Bot
parent cdde108af5
commit 4465ca296d
7 changed files with 21 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/compiler/glsl/gl_nir_lower_samplers_as_deref.c
View File

@ -236,7 +236,7 @@ record_textures_used(struct shader_info *info,
if (op == nir_texop_txf ||
op == nir_texop_txf_ms ||
op == nir_texop_txf_ms_mcs)
op == nir_texop_txf_ms_mcs_intel)
BITSET_SET_RANGE(info->textures_used_by_txf, var->data.binding, var->data.binding + (MAX2(size, 1) - 1));
}

14
src/compiler/nir/nir.h
View File

@ -2026,7 +2026,7 @@ typedef enum {
nir_tex_src_lod,
nir_tex_src_min_lod,
nir_tex_src_ms_index, /* MSAA sample index */
nir_tex_src_ms_mcs, /* MSAA compression value */
nir_tex_src_ms_mcs_intel, /* MSAA compression value */
nir_tex_src_ddx,
nir_tex_src_ddy,
nir_tex_src_texture_deref, /* < deref pointing to the texture */
@ -2052,7 +2052,7 @@ typedef enum {
nir_texop_txf, /**< Texel fetch with explicit LOD */
nir_texop_txf_ms, /**< Multisample texture fetch */
nir_texop_txf_ms_fb, /**< Multisample texture fetch from framebuffer */
nir_texop_txf_ms_mcs, /**< Multisample compression value fetch */
nir_texop_txf_ms_mcs_intel, /**< Multisample compression value fetch */
nir_texop_txs, /**< Texture size */
nir_texop_lod, /**< Texture lod query */
nir_texop_tg4, /**< Texture gather */
@ -2225,7 +2225,7 @@ nir_tex_instr_is_query(const nir_tex_instr *instr)
case nir_texop_txf:
case nir_texop_txf_ms:
case nir_texop_txf_ms_fb:
case nir_texop_txf_ms_mcs:
case nir_texop_txf_ms_mcs_intel:
case nir_texop_tg4:
return false;
default:
@ -2255,7 +2255,7 @@ nir_tex_instr_src_type(const nir_tex_instr *instr, unsigned src)
case nir_texop_txf:
case nir_texop_txf_ms:
case nir_texop_txf_ms_fb:
case nir_texop_txf_ms_mcs:
case nir_texop_txf_ms_mcs_intel:
case nir_texop_samples_identical:
return nir_type_int;
@ -2287,7 +2287,7 @@ nir_tex_instr_src_type(const nir_tex_instr *instr, unsigned src)
case nir_tex_src_plane:
return nir_type_int;
case nir_tex_src_ms_mcs:
case nir_tex_src_ms_mcs_intel:
case nir_tex_src_texture_deref:
case nir_tex_src_sampler_deref:
case nir_tex_src_texture_offset:
@ -2309,8 +2309,8 @@ nir_tex_instr_src_size(const nir_tex_instr *instr, unsigned src)
if (instr->src[src].src_type == nir_tex_src_coord)
return instr->coord_components;
/* The MCS value is expected to be a vec4 returned by a txf_ms_mcs */
if (instr->src[src].src_type == nir_tex_src_ms_mcs)
/* The MCS value is expected to be a vec4 returned by a txf_ms_mcs_intel */
if (instr->src[src].src_type == nir_tex_src_ms_mcs_intel)
return 4;
if (instr->src[src].src_type == nir_tex_src_ddx ||

8
src/compiler/nir/nir_print.c
View File

@ -1078,8 +1078,8 @@ print_tex_instr(nir_tex_instr *instr, print_state *state)
case nir_texop_txf_ms_fb:
fprintf(fp, "txf_ms_fb ");
break;
case nir_texop_txf_ms_mcs:
fprintf(fp, "txf_ms_mcs ");
case nir_texop_txf_ms_mcs_intel:
fprintf(fp, "txf_ms_mcs_intel ");
break;
case nir_texop_txs:
fprintf(fp, "txs ");
@ -1147,8 +1147,8 @@ print_tex_instr(nir_tex_instr *instr, print_state *state)
case nir_tex_src_ms_index:
fprintf(fp, "(ms_index)");
break;
case nir_tex_src_ms_mcs:
fprintf(fp, "(ms_mcs)");
case nir_tex_src_ms_mcs_intel:
fprintf(fp, "(ms_mcs_intel)");
break;
case nir_tex_src_ddx:
fprintf(fp, "(ddx)");

2
src/compiler/spirv/spirv_to_nir.c
View File

@ -2757,7 +2757,7 @@ vtn_handle_texture(struct vtn_builder *b, SpvOp opcode,
case nir_texop_txf_ms_fb:
vtn_fail("unexpected nir_texop_txf_ms_fb");
break;
case nir_texop_txf_ms_mcs:
case nir_texop_txf_ms_mcs_intel:
vtn_fail("unexpected nir_texop_txf_ms_mcs");
case nir_texop_tex_prefetch:
vtn_fail("unexpected nir_texop_tex_prefetch");

7
src/intel/blorp/blorp_blit.c
View File

@ -150,7 +150,8 @@ blorp_create_nir_tex_instr(nir_builder *b, struct brw_blorp_blit_vars *v,
* more explicit in the future.
*/
assert(pos->num_components >= 2);
if (op == nir_texop_txf || op == nir_texop_txf_ms || op == nir_texop_txf_ms_mcs) {
if (op == nir_texop_txf || op == nir_texop_txf_ms ||
op == nir_texop_txf_ms_mcs_intel) {
pos = nir_vec3(b, nir_channel(b, pos, 0), nir_channel(b, pos, 1),
nir_f2i32(b, nir_load_var(b, v->v_src_z)));
} else {
@ -227,7 +228,7 @@ blorp_nir_txf_ms(nir_builder *b, struct brw_blorp_blit_vars *v,
}
if (mcs) {
tex->src[2].src_type = nir_tex_src_ms_mcs;
tex->src[2].src_type = nir_tex_src_ms_mcs_intel;
tex->src[2].src = nir_src_for_ssa(mcs);
}
@ -241,7 +242,7 @@ blorp_blit_txf_ms_mcs(nir_builder *b, struct brw_blorp_blit_vars *v,
nir_ssa_def *pos)
{
nir_tex_instr *tex =
blorp_create_nir_tex_instr(b, v, nir_texop_txf_ms_mcs,
blorp_create_nir_tex_instr(b, v, nir_texop_txf_ms_mcs_intel,
pos, 1, nir_type_int);
tex->sampler_dim = GLSL_SAMPLER_DIM_MS;

2
src/intel/blorp/blorp_nir_builder.h
View File

@ -39,7 +39,7 @@ static inline nir_ssa_def *
blorp_nir_txf_ms_mcs(nir_builder *b, nir_ssa_def *xy_pos, nir_ssa_def *layer)
{
nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
tex->op = nir_texop_txf_ms_mcs;
tex->op = nir_texop_txf_ms_mcs_intel;
tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
tex->dest_type = nir_type_int32;

6
src/intel/compiler/brw_fs_nir.cpp
View File

@ -5879,7 +5879,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
switch (instr->op) {
case nir_texop_txf:
case nir_texop_txf_ms:
case nir_texop_txf_ms_mcs:
case nir_texop_txf_ms_mcs_intel:
case nir_texop_samples_identical:
srcs[TEX_LOGICAL_SRC_COORDINATE] = retype(src, BRW_REGISTER_TYPE_D);
break;
@ -5968,7 +5968,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
srcs[TEX_LOGICAL_SRC_SAMPLER_HANDLE] = bld.emit_uniformize(src);
break;
case nir_tex_src_ms_mcs:
case nir_tex_src_ms_mcs_intel:
assert(instr->op == nir_texop_txf_ms);
srcs[TEX_LOGICAL_SRC_MCS] = retype(src, BRW_REGISTER_TYPE_D);
break;
@ -6030,7 +6030,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
else
opcode = SHADER_OPCODE_TXF_CMS_LOGICAL;
break;
case nir_texop_txf_ms_mcs:
case nir_texop_txf_ms_mcs_intel:
opcode = SHADER_OPCODE_TXF_MCS_LOGICAL;
break;
case nir_texop_query_levels: