Commit Graph

108674 Commits

Author SHA1 Message Date
Kenneth Graunke 4801af2f26 iris: Do binder address allocations per-context, not globally.
iris_bufmgr allocates addresses across the entire screen, since buffers
may be shared between multiple contexts.  There used to be a single
special address, IRIS_BINDER_ADDRESS, that was per-context - and all
contexts used the same address.  When I moved to the multi-binder
system, I made a separate memory zone for them.  I wanted there to be
2-3 binders per context, so we could cycle them to avoid the stalls
inherent in pinning two buffers to the same address in back-to-back
batches.  But I figured I'd allow 100 binders just to be wildly
excessive/cautious.

What I didn't realize was that we need 2-3 binders per *context*,
and what I did was allocate 100 binders per *screen*.  Web browsers,
for example, might have 1-2 contexts per tab, leading to hundreds of
contexts, and thus binders.

To fix this, we stop allocating VMA for binders in bufmgr, and let
the binder handle it itself.  Binders are per-context, and they can
assign context-local addresses for the buffers by simply doing a
ringbuffer style approach.  We only hold on to one binder BO at a
time, so we won't ever have a conflicting address.

This fixes dEQP-EGL.functional.multicontext.non_shared_clear.

Huge thanks to Tapani Pälli for debugging this whole mess and
figuring out what was going wrong.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-02-21 10:26:11 -08:00
Kenneth Graunke 0f33204f05 iris: Fix memzone_for_address for the surface and binder zones
We use > for IRIS_MEMZONE_DYNAMIC because IRIS_BORDER_COLOR_POOL_ADDRESS
lives at the very start of that zone.  However, IRIS_MEMZONE_SURFACE and
IRIS_MEMZONE_BINDER are normal zones.  They used to be a single zone
(surface) with a single binder BO at the beginning, similar to the
border color pool.  But when I moved us to multiple binders, I made them
have a real zone (if a small one).  So both zones should use >=.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-02-21 10:26:11 -08:00
Kenneth Graunke 3bcb1a7fcd iris: Don't whack SO dirty bits when finishing a BLORP op
Re-emitting 3DSTATE_SO_BUFFERS can be hazardous, as it could zero
offsets.  Plus, it's just not necessary - BLORP doesn't change these.
2019-02-21 10:26:11 -08:00
Kenneth Graunke b9697dd820 iris: Fix SO issue with INTEL_DEBUG=reemit, set fewer bits
INTEL_DEBUG=reemit was breaking streamout tests, by re-emitting
3DSTATE_SO_BUFFER commands that tell the HW to zero the SO write
offsets.  We would need to alter them to use 0xFFFFFFFF for the offset.

Also, have each upload function only flag bits relevant to its own
pipeline.
2019-02-21 10:26:11 -08:00
Kenneth Graunke 61798e3c88 iris: CS stall on VF cache invalidate workarounds
See commit 31e4c9ce40 in i965.
2019-02-21 10:26:11 -08:00
Kenneth Graunke c81941f1e7 iris: Pay attention to blit masks
For combined depth/stencil formats, we may want to only blit one half.
If PIPE_BLIT_Z is set, blit depth; if PIPE_BLIT_S is set, blit stencil.
2019-02-21 10:26:11 -08:00
Kenneth Graunke 7837fec740 iris: Assert about blits with color masking
st/mesa never asks for this today, but in theory someone might, and we
don't support it.
2019-02-21 10:26:11 -08:00
Kenneth Graunke 0f677b0d87 iris: Don't enable smooth points when point sprites are enabled
dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_*.primitives.points
2019-02-21 10:26:11 -08:00
Kenneth Graunke 3b336a1513 iris: Allow sample mask of 0
I think this was an attempt to work around various sample mask bugs I
had early on.  It's not correct.  A sample mask of 0 is legal and means
to disable all samples.

Fixes dEQP-GLES31.functional.texture.multisample.*.*sample_mask*
2019-02-21 10:26:11 -08:00
Kenneth Graunke e17333ea1e iris: fail to create screen for older unsupported HW
loader shouldn't try, but let's be paranoid
2019-02-21 10:26:11 -08:00
Kenneth Graunke 1f91f688e8 iris: Switch to the new PIPELINE_STATISTICS_QUERY_SINGLE capability
I had a hack in place earlier to pass the query type as q->index
for the regular statistics query, but we ended up adjusting the
interface and adding a new query type.  Use that instead, fixing
pipeline statistics queries since the rebase.
2019-02-21 10:26:11 -08:00
Kenneth Graunke a23c06cabc iris: Use new PIPE_STAT_QUERY enums rather than hardcoded numbers. 2019-02-21 10:26:11 -08:00
Kenneth Graunke 5aef30b886 iris: Fix Broadwell WaDividePSInvocationCountBy4
We were dividing by 4 in calculate_result_on_gpu(), and also in
iris_get_query_result().  We should stop doing the latter, and instead
divide by 4 in calculate_result_on_cpu() as well.

Otherwise, if snapshots were available, and you hit the
calculate_result_on_cpu() path, but requested it be written to a QBO,
you'd fail to get a divide.
2019-02-21 10:26:11 -08:00
Kenneth Graunke 7f318bf2ac iris: Delete genx->bound_vertex_buffers
This is actually stored in ice->state, as it isn't gen-specific
2019-02-21 10:26:11 -08:00
Kenneth Graunke 02991e2878 iris: Drop a dead comment 2019-02-21 10:26:11 -08:00
Kenneth Graunke 572fad1e84 iris: Don't check other batches for our batch BO
This is an awkward corner case.  We create batches in order, each of
which creates and pins a BO.  The other batches may not be set up yet,
so it may not be safe to ask whether they reference a BO.

Just avoid this for now.  We could avoid it for other context-local BOs
too, but we currently don't have a flag for that (and I'm not certain
whether it's worth it).
2019-02-21 10:26:11 -08:00
Kenneth Graunke 8eda6f2288 iris: Handle PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE somewhat
Various places in the transfer code need to know whether they must
read the existing resource's values.  Rather than checking both flags
everywhere, just make PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE also flag
PIPE_TRANSFER_DISCARD_RANGE - if we can discard everything, we can
discard a subrange, too.

Obviously, we can do better for PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE,
but eventually u_threaded_context should handle swapping out buffers
for new idle buffers, anyway.  In the meantime, this is at least better.
2019-02-21 10:26:11 -08:00
Kenneth Graunke bacc722d13 iris: Flush the render cache in flush_and_dirty_for_history
BLORP uses the render engine to write to buffers, and we need to flush
that data out to the actual surface (finishing the write).  Then, the
rest of this function invalidates any caches that might have stale data
which needs to be refetched.
2019-02-21 10:26:11 -08:00
Kenneth Graunke 7a9e87c224 iris: Implement multi-slice copy_region
I don't know if this is required - surprisingly, I haven't seen it
matter - but I'd like to use it for multi-slice transfer maps.  We may
as well do the right thing.
2019-02-21 10:26:11 -08:00
Kenneth Graunke 307f3f9924 iris: Leave a comment about why Broadwell images are broken
There are a variety of ways to fix this, many of which are simple, but
I could use some advice on which ones other people prefer, and so we'll
punt until after the holidays.
2019-02-21 10:26:11 -08:00
Kenneth Graunke 7ed1383c0a iris: Fix surface states for Gen8 lowered-to-untype images
We have to use SURFTYPE_BUFFER and ISL_FORMAT_RAW for these.
2019-02-21 10:26:11 -08:00
Kenneth Graunke 477e7d575b iris: Fill out brw_image_params for storage images on Broadwell 2019-02-21 10:26:11 -08:00
Kenneth Graunke 7e35333c73 iris: Don't make duplicate system values
We were relying on CSE/GVN/etc to coalesce all intrinsics that load the
same value, but that's a bad idea.  We might have a couple intrinsics
that reload the same value.  If so, we only want to set up the uniform
on the first one we see.
2019-02-21 10:26:11 -08:00
Kenneth Graunke bc3bb28645 iris: Don't enable push constants just because there are system values
System values are built-in uniforms.  We set them up as UBO values, and
might pull or push them.  UBO push analysis will take care of that.  We
only want to enable push constants if there's an actual range being
pushed.  Otherwise, we might get into a scenario where 3DSTATE_PS
enables push constants but 3DSTATE_CONSTANT_PS isn't pushing anything.

This fixes GPU hangs in Broadwell image load store tests which have
unused image param system values but no other uniforms.  (We shouldn't
be making those anyway, but that's a separate fix...)
2019-02-21 10:26:11 -08:00
Kenneth Graunke 2ca0d913ea iris: Fix framebuffer layer count
cso_fb->layers is only valid for no-attachment framebuffers.  Use the
helper function to get the real value, then stash it so we don't have
to call the helper function on the old value for comparison, or at draw
time for Force Zero RTA Index setting.

This fixes Force Zero RTA Index being set even when attempting layered
rendering.
2019-02-21 10:26:11 -08:00
Dave Airlie df60241ff7 iris: handle qbo fragment shader invocation workaround 2019-02-21 10:26:11 -08:00
Dave Airlie 5ae2e5aa94 iris: add fs invocations query workaround for broadwell 2019-02-21 10:26:11 -08:00
Dave Airlie 8806b29e16 iris: setup gen8 caps 2019-02-21 10:26:11 -08:00
Dave Airlie 1bbf095473 iris: limit gen8 to 8 samples 2019-02-21 10:26:11 -08:00
Dave Airlie 823609b1a3 iris/WIP: add broadwell support
This adds all the state changes, MOCS changes,
2019-02-21 10:26:11 -08:00
Kenneth Graunke 5be72d9a20 iris: Delete bogus comment about cube array counting.
Both 'z' and 'depth' are counted in slices, according to the Gallium
docs (context.rst).  In our temporary memory, we allocate `box.depth`
slices, so we need to rebase the starting slice (box.z) down to 0,
and back again when writing on unmap.

There's nothing strange about cubes here.
2019-02-21 10:26:11 -08:00
Kenneth Graunke 73709be0c3 iris: Fix compute scratch pinning
Thanks to Eero Tamminen for helping catch this.
2019-02-21 10:26:11 -08:00
Kenneth Graunke 3ab3aa23c2 iris: Add a more long term TODO about timebase scaling 2019-02-21 10:26:11 -08:00
Kenneth Graunke 7ddc1f8ded iris: Only resolve inputs for actual shader stages
We don't need to consider compute at render time, and don't need to
consider disabled stages.  4% on drawoverhead.
2019-02-21 10:26:11 -08:00
Rhys Kidd 6c17e7d95f iris: Fix assertion in iris_resource_from_handle() tiling usage
Assertion error:

  iris_resource_from_handle: Assertion `res->bo->tiling_mode ==
      isl_tiling_to_i915_tiling(res->surf.tiling)' failed.

This patch fixes 16 piglit tests on KBL:
glx/glx-multithread-texture
glx/glx-query-drawable-glx_fbconfig_id-glxpbuffer
glx/glx-query-drawable-glx_fbconfig_id-glxpixmap
glx/glx-query-drawable-glx_preserved_contents
glx/glx-query-drawable-glxpbuffer-glx_height
glx/glx-query-drawable-glxpbuffer-glx_width
glx/glx-query-drawable-glxpixmap-glx_height
glx/glx-query-drawable-glxpixmap-glx_width
glx/glx-swap-pixmap
glx/glx-swap-pixmap-bad
glx/glx-tfp
glx/glx-visuals-depth -pixmap
glx/glx-visuals-stencil -pixmap
spec/egl 1.4/eglcreatepbuffersurface and then glclear
spec/egl 1.4/largest possible eglcreatepbuffersurface and then glclear
spec/egl_nok_texture_from_pixmap/basic

Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
2019-02-21 10:26:11 -08:00
Kenneth Graunke 73d525f188 iris: Fix scratch space allocation on Icelake.
Gen9-10 have fewer than 4 subslices per slice, so they need this to be
rounded up.  Gen11 isn't documented as needing this hack, and it can
also have more than 4 subslices, so the hack actually can break things.

Fixes tests/spec/arb_enhanced_layouts/execution/component-layout/
sso-vs-gs-fs-array-interleave
2019-02-21 10:26:11 -08:00
Kenneth Graunke 154e3e45bb iris: better MOCS 2019-02-21 10:26:11 -08:00
Dave Airlie aaaf611130 iris: fix gpu calcs for timestamp queries 2019-02-21 10:26:11 -08:00
Kenneth Graunke 3c45d03049 iris: only mark depth/stencil as writable if writes are actually enabled 2019-02-21 10:26:11 -08:00
Kenneth Graunke 3a938a4b23 iris: more dead comments 2019-02-21 10:26:11 -08:00
Kenneth Graunke e169cb09c3 iris: pin and re-pin the scratch BO 2019-02-21 10:26:11 -08:00
Kenneth Graunke dd0d47a5d2 iris: delete finished comments 2019-02-21 10:26:11 -08:00
Kenneth Graunke 32ee2e4c27 iris: always pin the binder...in the compute context, too.
not sure why this hasn't tripped things up
2019-02-21 10:26:11 -08:00
Kenneth Graunke fbfe07c4f3 iris: Track blend enables, save outbound for resolve code 2019-02-21 10:26:11 -08:00
Kenneth Graunke 5481887ca8 iris: whitespace fixes 2019-02-21 10:26:11 -08:00
Kenneth Graunke b2fa90706e iris: Make a alloc_surface_state helper
This does the gtt_offset addition for us
2019-02-21 10:26:11 -08:00
Kenneth Graunke b358c4b92b iris: Use a surface state fill helper
This will check aux_usage eventually
2019-02-21 10:26:11 -08:00
Kenneth Graunke b92ca4d0f6 iris: don't print the pointer in INTEL_DEBUG=submit
lots of noise in diff, hope was it would be useful for gdb, but the
the GEM handle is good enough
2019-02-21 10:26:11 -08:00
Kenneth Graunke ad969a00c0 iris: Fix the prototype for iris_bo_alloc_tiled
This now matches the actual function in iris_bufmgr.c, as well as the
equivalent brw_bufmgr.c function...
2019-02-21 10:26:11 -08:00
Kenneth Graunke 598a78849e iris: Fix for PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
This fixes ext_transform_feedback-builtin-varyings gl_Position after the
combination of my transform feedback reworks and my vertex buffer
reworks (?)
2019-02-21 10:26:11 -08:00