Eric Engestrom
ed07e831a8
i965: gen_shader_sha1() doesn't use the brw_context
...
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-08-07 14:20:50 +01:00
Eric Engestrom
87c156183c
configure: install KHR/khrplatform.h when needed
...
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107511
Fixes: f7d42ee7d3
"include: update GL & GLES headers (v2)"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Brad King <brad.king@kitware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-07 14:20:50 +01:00
Lionel Landwerlin
303e7b39b5
intel: don't build tools without -Dtools=intel
...
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107487
Fixes: 4334196ab325c6w ("intel: tools: simplify meson build")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-07 11:58:47 +01:00
Erik Faye-Lund
c4f183492d
virgl: update virgl_hw.h from virglrenderer
...
This just makes sure we're currently up-to-date with what
virglrenderer has.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2018-08-07 09:38:41 +02:00
Erik Faye-Lund
0914e1464e
virgl: rename msaa_sample_positions -> sample_locations
...
This matches what this field is called in virglrenderer's copy of
this.
This reduces the diff between the two different versions of
virgl_hw.h, and should make it easier to upgrade the file in
the future.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2018-08-07 09:38:27 +02:00
Eric Anholt
9507e03699
vc4: Fix a leak of the no-vertex-elements workaround BO.
...
Fixes: bd1925562a
("vc4: Convert the driver to emitting the shader record using pack macros.")
2018-08-06 19:10:06 -07:00
Eric Anholt
86095e9bb1
vc4: Fix context creation when syncobjs aren't supported.
...
Noticed when trying to run current Mesa on rpi's downstream kernel.
Fixes: b0acc3a562
("broadcom/vc4: Native fence fd support")
2018-08-06 19:10:06 -07:00
Eric Anholt
1561e4984e
v3d: Emit the VCM_CACHE_SIZE packet.
...
This is needed to ensure that we don't get blocked waiting for VPM space
with bin/render overlapping.
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
2018-08-06 13:03:23 -07:00
Eric Anholt
5d49076990
v3d: Drop "VC5" from the renderer string.
...
VC5 isn't a useful name any more, just stick to v3d.
2018-08-06 13:03:23 -07:00
Eric Anholt
50a8713d4f
v3d: Avoid spilling that breaks the r5 usage after a ldvary.
...
Fixes bad rendering when forcing 2 spills in glxgears.
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
2018-08-06 13:03:23 -07:00
Eric Anholt
f2c0d310d6
v3d: Make sure that QPU instruction-has-a-dest matches VIR.
...
Found when debugging register spilling -- we would try to spill the dest
of a STVPMV, inserting spill code after entering the last segment. In
fact, we were likely to to choose to do this, given that the STVPMV "dest"
temp was never read from, making it cheap to spill.
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
2018-08-06 13:03:23 -07:00
Eric Anholt
3f9cb2eb05
v3d: Wait for TMU writes to complete before continuing after a spill.
...
The simulator complained that we had write responses outstanding at shader
end. It seems that a TMU read does not guarantee that previous TMU writes
by the thread have completed, which surprised me.
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
2018-08-06 13:03:23 -07:00
Eric Anholt
ccbe33af5b
v3d: Make sure we don't emit a thrsw before the last one finished.
...
Found while forcing some spilling, which creates a lot of short
tmua->thrsw->ldtmu sequences.
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
2018-08-06 13:03:23 -07:00
Eric Anholt
f9d54dc3cf
v3d: Add some debug code for forcing register spilling.
...
This is useful for periodically testing out register spilling to see how
it goes on simple shaders, rather than only failing on insanely
complicated ones.
2018-08-06 13:03:23 -07:00
Chad Versace
aaa41cd297
drisw: Fix build on Android Nougat, which lacks shm (v2)
...
In commit cf54bd5e8
, dri_sw_winsys.c began using <sys/shm.h> to support
the new functions putImageShm, getImageShm in DRI_SWRastLoader. But
Android began supporting System V shared memory only in Oreo. Nougat has
no shm headers.
Fix the build by ifdef'ing out the shm code on Nougat.
Fixes: cf54bd5e8
"drisw: use shared memory when possible"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: Marc-André Lureau <marcandre.lureau@gmail.com>
2018-08-06 11:09:38 -07:00
Ian Romanick
6229ee87c7
mesa: fix make check for AMD_framebuffer_multisample_advanced
...
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107483
Fixes: 3d6900d76e
("glapi: define AMD_framebuffer_multisample_advanced and add its functions")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Vinson Lee <vlee@freedesktop.org>
2018-08-06 10:31:56 -07:00
Ian Romanick
b7946f6778
glapi: Fix GLES versioning for AMD_framebuffer_multisample_advanced functions
...
The GL_AMD_framebuffer_multisample_advanced spec says:
OpenGL ES dependencies:
Requires OpenGL ES 3.0.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107483
Fixes: 3d6900d76e
("glapi: define AMD_framebuffer_multisample_advanced and add its functions")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Vinson Lee <vlee@freedesktop.org>
2018-08-06 10:30:06 -07:00
Gert Wollny
7a46b2d641
meson, install_megadrivers: Also remove stale symlinks
...
os.path.exists doesn't return True for stale symlinks, but they are in
the way later, when a link/file with the same name is to be created.
For instance it is conceivable that the pointed to file is replaced by
a file with a new name, and then the symlink is dead.
To handle this check specifically for all existing symlinks to be
removed. (This bugged me for some time with a link libXvMCr600.so
always being in the way of installing this file)
v2: use only os.lexist and replace all instances of os.exist (Dylan Baker)
v3: handle directory check correctly (Eric Engestrom)
Fixes: f7f1b30f81
("meson: extend install_megadrivers script to handle symmlinking")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>(v2 minus dir check)
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
2018-08-06 18:42:01 +02:00
Tapani Pälli
5eb4b384d9
anv: add more swapchain formats
...
This change helps with some of the dEQP-VK.wsi.android.* tests that
try to create swapchain with using such formats.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2018-08-06 09:25:11 +03:00
Karol Herbst
c3325097be
nvc0/ir: return 0 in imageLoad on incomplete textures
...
We already guarded all OP_SULDP against out of bound accesses, but we
ended up just reusing whatever value was stored in the dest registers.
Fixes CTS test shader_image_load_store.incomplete_textures
v2: fix for loads not ending up with predicates (bindless_texture)
v3: fix replacing the def
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2018-08-04 18:25:20 +02:00
Karol Herbst
0ca046d7e9
gm200/ir: optimize rcp(sqrt) to rsq
...
mitigates hurt shaders after adding sqrt:
total instructions in shared programs : 5456166 -> 5454825 (-0.02%)
total gprs used in shared programs : 647522 -> 647551 (0.00%)
total shared used in shared programs : 389120 -> 389120 (0.00%)
total local used in shared programs : 21064 -> 21064 (0.00%)
total bytes used in shared programs : 58288696 -> 58274448 (-0.02%)
local shared gpr inst bytes
helped 0 0 0 516 516
hurt 0 0 27 2 2
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2018-08-04 15:24:08 +02:00
Karol Herbst
6f98a3065b
gm200/ir: add native OP_SQRT support
...
./GpuTest /test=pixmark_piano 1024x640 30sec:
301 -> 327 points
shader-db:
total instructions in shared programs : 5472103 -> 5456166 (-0.29%)
total gprs used in shared programs : 647530 -> 647522 (-0.00%)
total shared used in shared programs : 389120 -> 389120 (0.00%)
total local used in shared programs : 21064 -> 21064 (0.00%)
total bytes used in shared programs : 58459304 -> 58288696 (-0.29%)
local shared gpr inst bytes
helped 0 0 27 8281 8281
hurt 0 0 21 431 431
v2: use NVISA_GM200_CHIPSET
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2018-08-04 15:24:08 +02:00
Lionel Landwerlin
4334196ab3
intel: tools: simplify meson build
...
Remove the if tools condition and just put it through the install:
parameter.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-04 09:45:34 +01:00
Lionel Landwerlin
87a3c97781
intel: aubinator: simplify decoding
...
Since we don't support streaming an aub file, we can drop the decoding
status enum.
v2: include stdbool (Eric)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-04 09:40:14 +01:00
Lionel Landwerlin
02ebc064ea
intel: common: add missing stdint include
...
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-04 09:39:01 +01:00
Lionel Landwerlin
db4770ee57
intel: decoder: remove unused variable
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-04 09:38:58 +01:00
Lionel Landwerlin
7471286bb0
intel: tools: aubwrite: reuse canonical address helper
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-04 09:38:44 +01:00
Lionel Landwerlin
35955afa7a
intel: aubinator: fix read the context/ring
...
Up to now we've been lucky that the buffer returned was always exactly
at the address we requested.
Fixes: 144b40db54
("intel: aubinator: drop the 1Tb GTT mapping")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-08-04 09:38:34 +01:00
Ian Romanick
3b07d28f81
nir: Transform expressions of b2f(a) and b2f(b) to a == b
...
All Gen7+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 14276886 -> 14276838 (<.01%)
instructions in affected programs: 312 -> 264 (-15.38%)
helped: 2
HURT: 0
total cycles in shared programs: 532578395 -> 532570985 (<.01%)
cycles in affected programs: 682562 -> 675152 (-1.09%)
helped: 374
HURT: 4
helped stats (abs) min: 2 max: 200 x̄: 20.39 x̃: 18
helped stats (rel) min: 0.07% max: 11.64% x̄: 1.25% x̃: 1.28%
HURT stats (abs) min: 2 max: 114 x̄: 53.50 x̃: 49
HURT stats (rel) min: 0.06% max: 11.70% x̄: 5.02% x̃: 4.15%
95% mean confidence interval for cycles value: -21.30 -17.91
95% mean confidence interval for cycles %-change: -1.30% -1.06%
Cycles are helped.
Sandy Bridge
total instructions in shared programs: 10488123 -> 10488075 (<.01%)
instructions in affected programs: 336 -> 288 (-14.29%)
helped: 2
HURT: 0
total cycles in shared programs: 150260379 -> 150260439 (<.01%)
cycles in affected programs: 4726 -> 4786 (1.27%)
helped: 0
HURT: 2
No changes on Iron Lake or GM45.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Ian Romanick
c658b6c4c8
nir: Transform expressions of b2f(a) and b2f(b) to a ^^ b
...
All Gen platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14276892 -> 14276886 (<.01%)
instructions in affected programs: 484 -> 478 (-1.24%)
helped: 2
HURT: 0
total cycles in shared programs: 532578397 -> 532578395 (<.01%)
cycles in affected programs: 3522 -> 3520 (-0.06%)
helped: 1
HURT: 0
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Ian Romanick
3aca80aabc
nir: Transform expressions of b2f(a) and b2f(b) to !(a && b)
...
All Gen platforms had pretty similar results. (Skylake shown)
total cycles in shared programs: 532578400 -> 532578397 (<.01%)
cycles in affected programs: 2784 -> 2781 (-0.11%)
helped: 1
HURT: 1
helped stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
helped stats (rel) min: 0.26% max: 0.26% x̄: 0.26% x̃: 0.26%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.08% max: 0.08% x̄: 0.08% x̃: 0.08%
v2: s/fmax/fmin/. Noticed by Thomas Helland.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Ian Romanick
1713c97181
nir: Transform expressions of b2f(a) and b2f(b) to a && b
...
No changes on any Gen platform.
v2: s/fmax/fmin/. Noticed by Thomas Helland.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Ian Romanick
4425f4786a
nir: Transform expressions of b2f(a) and b2f(b) to !(a || b)
...
All Gen6+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 14276961 -> 14276892 (<.01%)
instructions in affected programs: 3215 -> 3146 (-2.15%)
helped: 28
HURT: 0
helped stats (abs) min: 1 max: 6 x̄: 2.46 x̃: 2
helped stats (rel) min: 0.47% max: 9.52% x̄: 4.34% x̃: 1.92%
95% mean confidence interval for instructions value: -2.87 -2.06
95% mean confidence interval for instructions %-change: -5.73% -2.95%
Instructions are helped.
total cycles in shared programs: 532577068 -> 532578400 (<.01%)
cycles in affected programs: 121864 -> 123196 (1.09%)
helped: 35
HURT: 30
helped stats (abs) min: 2 max: 268 x̄: 42.34 x̃: 22
helped stats (rel) min: 0.12% max: 12.14% x̄: 3.22% x̃: 1.86%
HURT stats (abs) min: 2 max: 246 x̄: 93.80 x̃: 36
HURT stats (rel) min: 0.09% max: 13.63% x̄: 4.47% x̃: 2.58%
95% mean confidence interval for cycles value: -5.02 46.01
95% mean confidence interval for cycles %-change: -0.99% 1.65%
Inconclusive result (value mean confidence interval includes 0).
Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 7781299 -> 7781342 (<.01%)
instructions in affected programs: 22300 -> 22343 (0.19%)
helped: 13
HURT: 40
helped stats (abs) min: 2 max: 3 x̄: 2.85 x̃: 3
helped stats (rel) min: 1.15% max: 7.69% x̄: 3.72% x̃: 3.33%
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.26% max: 1.30% x̄: 0.47% x̃: 0.43%
95% mean confidence interval for instructions value: 0.23 1.39
95% mean confidence interval for instructions %-change: -1.18% 0.07%
Inconclusive result (%-change mean confidence interval includes 0).
total cycles in shared programs: 177878928 -> 177879332 (<.01%)
cycles in affected programs: 383298 -> 383702 (0.11%)
helped: 7
HURT: 43
helped stats (abs) min: 2 max: 18 x̄: 10.00 x̃: 10
helped stats (rel) min: 0.17% max: 4.81% x̄: 2.62% x̃: 3.40%
HURT stats (abs) min: 2 max: 38 x̄: 11.02 x̃: 12
HURT stats (rel) min: 0.08% max: 1.54% x̄: 0.25% x̃: 0.09%
95% mean confidence interval for cycles value: 5.21 10.95
95% mean confidence interval for cycles %-change: -0.51% 0.21%
Inconclusive result (%-change mean confidence interval includes 0).
v2: s/fmin/fmax/. Noticed by Thomas Helland.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Ian Romanick
6b3670ae80
nir: Transform -fabs(a) >= 0 to a == 0
...
All Gen platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14276964 -> 14276961 (<.01%)
instructions in affected programs: 411 -> 408 (-0.73%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.47% max: 1.96% x̄: 1.04% x̃: 0.68%
total cycles in shared programs: 532577062 -> 532577068 (<.01%)
cycles in affected programs: 1093 -> 1099 (0.55%)
helped: 1
HURT: 1
helped stats (abs) min: 16 max: 16 x̄: 16.00 x̃: 16
helped stats (rel) min: 7.77% max: 7.77% x̄: 7.77% x̃: 7.77%
HURT stats (abs) min: 22 max: 22 x̄: 22.00 x̃: 22
HURT stats (rel) min: 2.48% max: 2.48% x̄: 2.48% x̃: 2.48%
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Ian Romanick
46e7c340d4
nir: Transform expressions of b2f(a) and b2f(b) to a || b
...
All Gen6+ platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14277184 -> 14276964 (<.01%)
instructions in affected programs: 10082 -> 9862 (-2.18%)
helped: 37
HURT: 1
helped stats (abs) min: 1 max: 30 x̄: 5.97 x̃: 4
helped stats (rel) min: 0.14% max: 16.00% x̄: 5.23% x̃: 2.04%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.70% max: 0.70% x̄: 0.70% x̃: 0.70%
95% mean confidence interval for instructions value: -7.87 -3.71
95% mean confidence interval for instructions %-change: -6.98% -3.16%
Instructions are helped.
total cycles in shared programs: 532577990 -> 532577062 (<.01%)
cycles in affected programs: 170959 -> 170031 (-0.54%)
helped: 33
HURT: 9
helped stats (abs) min: 2 max: 120 x̄: 30.91 x̃: 30
helped stats (rel) min: 0.02% max: 7.65% x̄: 2.66% x̃: 1.13%
HURT stats (abs) min: 2 max: 24 x̄: 10.22 x̃: 8
HURT stats (rel) min: 0.09% max: 1.79% x̄: 0.61% x̃: 0.22%
95% mean confidence interval for cycles value: -31.23 -12.96
95% mean confidence interval for cycles %-change: -2.90% -1.02%
Cycles are helped.
Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 7781539 -> 7781301 (<.01%)
instructions in affected programs: 10169 -> 9931 (-2.34%)
helped: 32
HURT: 0
helped stats (abs) min: 2 max: 20 x̄: 7.44 x̃: 6
helped stats (rel) min: 0.47% max: 17.02% x̄: 4.03% x̃: 1.88%
95% mean confidence interval for instructions value: -9.53 -5.34
95% mean confidence interval for instructions %-change: -5.94% -2.12%
Instructions are helped.
total cycles in shared programs: 177878590 -> 177878932 (<.01%)
cycles in affected programs: 78706 -> 79048 (0.43%)
helped: 7
HURT: 21
helped stats (abs) min: 6 max: 34 x̄: 24.57 x̃: 28
helped stats (rel) min: 0.15% max: 8.33% x̄: 4.66% x̃: 6.37%
HURT stats (abs) min: 2 max: 86 x̄: 24.48 x̃: 22
HURT stats (rel) min: 0.01% max: 4.28% x̄: 1.21% x̃: 0.70%
95% mean confidence interval for cycles value: 0.30 24.13
95% mean confidence interval for cycles %-change: -1.52% 1.01%
Inconclusive result (%-change mean confidence interval includes 0).
v2: s/fmin/fmax/. Noticed by Thomas Helland.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Ian Romanick
be7d3ba34a
nir: Transform -fabs(a) < 0 to a != 0
...
Unlike the much older -abs(a) >= 0.0 transformation, this is not
precise. The behavior changes if a is NaN.
All Gen platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14277216 -> 14277184 (<.01%)
instructions in affected programs: 2300 -> 2268 (-1.39%)
helped: 8
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 4.00 x̃: 3
helped stats (rel) min: 0.48% max: 15.15% x̄: 4.41% x̃: 1.01%
95% mean confidence interval for instructions value: -6.45 -1.55
95% mean confidence interval for instructions %-change: -9.96% 1.13%
Inconclusive result (%-change mean confidence interval includes 0).
total cycles in shared programs: 532577848 -> 532577990 (<.01%)
cycles in affected programs: 17486 -> 17628 (0.81%)
helped: 2
HURT: 5
helped stats (abs) min: 2 max: 6 x̄: 4.00 x̃: 4
helped stats (rel) min: 0.06% max: 1.81% x̄: 0.93% x̃: 0.93%
HURT stats (abs) min: 6 max: 50 x̄: 30.00 x̃: 26
HURT stats (rel) min: 0.55% max: 2.17% x̄: 1.19% x̃: 1.02%
95% mean confidence interval for cycles value: -1.06 41.63
95% mean confidence interval for cycles %-change: -0.58% 1.74%
Inconclusive result (value mean confidence interval includes 0).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Ian Romanick
d49eab2757
nir: Rearrange bcsel with two bcsel sources
...
All Gen platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14277220 -> 14277216 (<.01%)
instructions in affected programs: 422 -> 418 (-0.95%)
helped: 2
HURT: 0
total cycles in shared programs: 532577908 -> 532577848 (<.01%)
cycles in affected programs: 2800 -> 2740 (-2.14%)
helped: 2
HURT: 0
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Ian Romanick
b92fded6eb
nir: Collapse more repeated bcsels on the same argument
...
All Gen platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14277230 -> 14277220 (<.01%)
instructions in affected programs: 751 -> 741 (-1.33%)
helped: 4
HURT: 0
helped stats (abs) min: 2 max: 3 x̄: 2.50 x̃: 2
helped stats (rel) min: 1.23% max: 1.40% x̄: 1.32% x̃: 1.32%
95% mean confidence interval for instructions value: -3.42 -1.58
95% mean confidence interval for instructions %-change: -1.47% -1.17%
Instructions are helped.
total cycles in shared programs: 532577947 -> 532577908 (<.01%)
cycles in affected programs: 10641 -> 10602 (-0.37%)
helped: 4
HURT: 3
helped stats (abs) min: 1 max: 40 x̄: 13.75 x̃: 7
helped stats (rel) min: 0.11% max: 3.08% x̄: 1.10% x̃: 0.60%
HURT stats (abs) min: 2 max: 8 x̄: 5.33 x̃: 6
HURT stats (rel) min: 0.13% max: 0.55% x̄: 0.30% x̃: 0.23%
95% mean confidence interval for cycles value: -20.69 9.55
95% mean confidence interval for cycles %-change: -1.63% 0.63%
Inconclusive result (value mean confidence interval includes 0).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-08-04 01:12:03 -07:00
Ian Romanick
408330ed48
nir: Don't compare i2f or u2i with zero
...
Broadwell and Skylake had similar results. (Skylake shown)
total instructions in shared programs: 14277620 -> 14277230 (<.01%)
instructions in affected programs: 36905 -> 36515 (-1.06%)
helped: 101
HURT: 6
helped stats (abs) min: 1 max: 6 x̄: 4.46 x̃: 6
helped stats (rel) min: 0.32% max: 7.69% x̄: 1.80% x̃: 1.51%
HURT stats (abs) min: 1 max: 28 x̄: 10.00 x̃: 1
HURT stats (rel) min: 0.33% max: 1.74% x̄: 0.68% x̃: 0.47%
95% mean confidence interval for instructions value: -4.59 -2.70
95% mean confidence interval for instructions %-change: -1.90% -1.41%
Instructions are helped.
total cycles in shared programs: 532580716 -> 532577947 (<.01%)
cycles in affected programs: 940575 -> 937806 (-0.29%)
helped: 92
HURT: 12
helped stats (abs) min: 2 max: 158 x̄: 51.04 x̃: 62
helped stats (rel) min: 0.24% max: 3.99% x̄: 2.14% x̃: 2.41%
HURT stats (abs) min: 10 max: 1112 x̄: 160.58 x̃: 63
HURT stats (rel) min: 0.06% max: 21.90% x̄: 4.22% x̃: 0.20%
95% mean confidence interval for cycles value: -50.66 -2.59
95% mean confidence interval for cycles %-change: -2.09% -0.73%
Cycles are helped.
total spills in shared programs: 8116 -> 8124 (0.10%)
spills in affected programs: 200 -> 208 (4.00%)
helped: 0
HURT: 2
total fills in shared programs: 11086 -> 11094 (0.07%)
fills in affected programs: 436 -> 444 (1.83%)
helped: 0
HURT: 2
Ivy Bridge and Haswell had similar results. (Haswell shown)
total instructions in shared programs: 12979054 -> 12978067 (<.01%)
instructions in affected programs: 33633 -> 32646 (-2.93%)
helped: 120
HURT: 2
helped stats (abs) min: 1 max: 13 x̄: 8.53 x̃: 13
helped stats (rel) min: 0.30% max: 16.67% x̄: 4.55% x̃: 3.17%
HURT stats (abs) min: 18 max: 18 x̄: 18.00 x̃: 18
HURT stats (rel) min: 1.15% max: 2.84% x̄: 2.00% x̃: 2.00%
95% mean confidence interval for instructions value: -9.19 -6.99
95% mean confidence interval for instructions %-change: -5.27% -3.62%
Instructions are helped.
total cycles in shared programs: 411212880 -> 411199636 (<.01%)
cycles in affected programs: 696441 -> 683197 (-1.90%)
helped: 107
HURT: 5
helped stats (abs) min: 2 max: 864 x̄: 124.90 x̃: 146
helped stats (rel) min: 0.03% max: 29.20% x̄: 8.58% x̃: 5.88%
HURT stats (abs) min: 2 max: 50 x̄: 24.00 x̃: 22
HURT stats (rel) min: 0.01% max: 5.35% x̄: 1.29% x̃: 0.25%
95% mean confidence interval for cycles value: -136.96 -99.54
95% mean confidence interval for cycles %-change: -9.75% -6.53%
Cycles are helped.
total spills in shared programs: 78623 -> 78631 (0.01%)
spills in affected programs: 66 -> 74 (12.12%)
helped: 0
HURT: 2
total fills in shared programs: 80104 -> 80108 (<.01%)
fills in affected programs: 133 -> 137 (3.01%)
helped: 0
HURT: 2
No changes on Sandy Bridge, Iron Lake, or GM45.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Ian Romanick
a3845616a2
nir: Remove f2i(i2f(x)) conversions
...
Broadwell and Skylake had similar results. (Skylake shown)
total instructions in shared programs: 14277978 -> 14277620 (<.01%)
instructions in affected programs: 36957 -> 36599 (-0.97%)
helped: 76
HURT: 1
helped stats (abs) min: 2 max: 90 x̄: 4.89 x̃: 4
helped stats (rel) min: 0.44% max: 5.88% x̄: 1.04% x̃: 0.87%
HURT stats (abs) min: 14 max: 14 x̄: 14.00 x̃: 14
HURT stats (rel) min: 0.36% max: 0.36% x̄: 0.36% x̃: 0.36%
95% mean confidence interval for instructions value: -7.06 -2.24
95% mean confidence interval for instructions %-change: -1.28% -0.77%
Instructions are helped.
total cycles in shared programs: 532584581 -> 532580716 (<.01%)
cycles in affected programs: 973591 -> 969726 (-0.40%)
helped: 76
HURT: 1
helped stats (abs) min: 2 max: 9940 x̄: 159.80 x̃: 32
helped stats (rel) min: <.01% max: 8.70% x̄: 1.15% x̃: 1.19%
HURT stats (abs) min: 8280 max: 8280 x̄: 8280.00 x̃: 8280
HURT stats (rel) min: 2.10% max: 2.10% x̄: 2.10% x̃: 2.10%
95% mean confidence interval for cycles value: -386.98 286.59
95% mean confidence interval for cycles %-change: -1.41% -0.81%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 8127 -> 8116 (-0.14%)
spills in affected programs: 108 -> 97 (-10.19%)
helped: 1
HURT: 0
total fills in shared programs: 11090 -> 11086 (-0.04%)
fills in affected programs: 440 -> 436 (-0.91%)
helped: 1
HURT: 1
Haswell
total instructions in shared programs: 12979174 -> 12979054 (<.01%)
instructions in affected programs: 9040 -> 8920 (-1.33%)
helped: 14
HURT: 1
helped stats (abs) min: 2 max: 34 x̄: 8.79 x̃: 6
helped stats (rel) min: 0.41% max: 7.04% x̄: 2.66% x̃: 1.14%
HURT stats (abs) min: 3 max: 3 x̄: 3.00 x̃: 3
HURT stats (rel) min: 0.19% max: 0.19% x̄: 0.19% x̃: 0.19%
95% mean confidence interval for instructions value: -13.58 -2.42
95% mean confidence interval for instructions %-change: -3.94% -1.01%
Instructions are helped.
total cycles in shared programs: 411227148 -> 411212880 (<.01%)
cycles in affected programs: 630506 -> 616238 (-2.26%)
helped: 15
HURT: 0
helped stats (abs) min: 2 max: 11192 x̄: 951.20 x̃: 38
helped stats (rel) min: <.01% max: 16.01% x̄: 3.92% x̃: 0.17%
95% mean confidence interval for cycles value: -2544.28 641.88
95% mean confidence interval for cycles %-change: -6.89% -0.94%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 78626 -> 78623 (<.01%)
spills in affected programs: 42 -> 39 (-7.14%)
helped: 1
HURT: 0
total fills in shared programs: 80111 -> 80104 (<.01%)
fills in affected programs: 140 -> 133 (-5.00%)
helped: 1
HURT: 1
Ivy Bridge
total instructions in shared programs: 11684101 -> 11684030 (<.01%)
instructions in affected programs: 3080 -> 3009 (-2.31%)
helped: 4
HURT: 1
helped stats (abs) min: 5 max: 59 x̄: 18.50 x̃: 5
helped stats (rel) min: 6.47% max: 7.04% x̄: 6.87% x̃: 6.99%
HURT stats (abs) min: 3 max: 3 x̄: 3.00 x̃: 3
HURT stats (rel) min: 0.15% max: 0.15% x̄: 0.15% x̃: 0.15%
95% mean confidence interval for instructions value: -45.59 17.19
95% mean confidence interval for instructions %-change: -9.38% -1.56%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 258407697 -> 258389653 (<.01%)
cycles in affected programs: 328323 -> 310279 (-5.50%)
helped: 5
HURT: 0
helped stats (abs) min: 32 max: 14908 x̄: 3608.80 x̃: 32
helped stats (rel) min: 1.26% max: 17.22% x̄: 9.30% x̃: 10.60%
95% mean confidence interval for cycles value: -11616.71 4399.11
95% mean confidence interval for cycles %-change: -16.56% -2.03%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 4537 -> 4528 (-0.20%)
spills in affected programs: 64 -> 55 (-14.06%)
helped: 1
HURT: 0
total fills in shared programs: 4823 -> 4815 (-0.17%)
fills in affected programs: 189 -> 181 (-4.23%)
helped: 1
HURT: 1
Sandy Bridge
total instructions in shared programs: 10488464 -> 10488449 (<.01%)
instructions in affected programs: 272 -> 257 (-5.51%)
helped: 3
HURT: 0
helped stats (abs) min: 5 max: 5 x̄: 5.00 x̃: 5
helped stats (rel) min: 5.49% max: 5.56% x̄: 5.51% x̃: 5.49%
total cycles in shared programs: 150263359 -> 150263263 (<.01%)
cycles in affected programs: 7978 -> 7882 (-1.20%)
helped: 3
HURT: 0
helped stats (abs) min: 32 max: 32 x̄: 32.00 x̃: 32
helped stats (rel) min: 1.15% max: 1.23% x̄: 1.20% x̃: 1.23%
No changes on Iron Lake or GM45.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Ian Romanick
ea6c276436
nir: Mark the 0.0 < abs(a) transformation as imprecise
...
Unlike the much older -abs(a) >= 0.0 transformation, this is not
precise. The behavior changes if the source is NaN.
No shader-db changes on any platform.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-08-04 01:12:03 -07:00
Marek Olšák
4bad50ded9
radeonsi: cosmetic changes
2018-08-04 03:10:30 -04:00
Marek Olšák
6508b93d78
st/mesa: expose & set limits for AMD_framebuffer_multisample_advanced
...
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-08-04 02:47:58 -04:00
Marek Olšák
7f587b57f7
st/mesa: add renderbuffer support for AMD_framebuffer_multisample_advanced
...
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-08-04 02:46:55 -04:00
Marek Olšák
8e3d0019e1
st/mesa: pass storage_sample_count parameter into st_choose_format
...
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-08-04 02:46:55 -04:00
Marek Olšák
459f05c7ec
mesa: add functional FBO changes for AMD_framebuffer_multisample_advanced
...
- relax FBO completeness rules
- validate sample counts
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-08-04 02:46:55 -04:00
Marek Olšák
328c1c8d99
mesa: add gl_renderbuffer::NumStorageSamples
...
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-08-04 02:46:55 -04:00
Marek Olšák
a96e946d25
mesa: implement glGet for AMD_framebuffer_multisample_advanced
...
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-08-04 02:46:55 -04:00
Marek Olšák
3d6900d76e
glapi: define AMD_framebuffer_multisample_advanced and add its functions
...
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-08-04 02:46:55 -04:00
Marek Olšák
2d115056d3
mesa: add storageSamples parameter to renderbuffer functions
...
It's just passed to other functions but otherwise unused.
It will be used in following commits.
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-08-04 02:46:55 -04:00