Bifrost has a new type of job called 'index-driven vertex', which takes
in two shaders. The primary shader, called for all values, performs
position shading to a cacheline-aligned attribute buffer. The secondary
shader, called for values still live after culling, performs varying
shading.
It is the responsiblilty of the implementation to ensure that vertices
from different instances do not share a cacheline.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11413>
We can actually create array surfaces instead of requiring single-slice
in a few cases. This does require us to be very careful about our
checks, though.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11647>
It doesn't matter for the actual copy rectangle and this makes the
asserts a bit nicer as we don't need to bother with the intratile
offsets because there aren't any yet.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11647>
This adds a helper isl_surf_get_uncompressed_surf for creating a surface
which provides an uncompressed view into a compressed surface. The code
is basically a direct port of the uncompressed surface code from the
Vulkan driver which, in turn, was a port from BLORP.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11647>
Mirroring a change in iris; see the previous commit for rationale.
One difference is that crocus does sometimes use CPU maps on Atoms
for *reads*...but writes don't go through CPU caches. Should be OK.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11727>
Back when SSBOs were first enabled in i965, we tried to work around
issues where the CPU and GPU were incoherently writing to the same
cacheline by forcing an alignment such that different sections of
data would fall in different cachelines. This seems wrong.
On integrated GPUs with LLC, CPU and GPU writes should be coherent.
On integrated GPUs without LLC, we either enable snooping (so they
are again coherent), or we use WC maps (so the CPU cache isn't used).
Discrete GPUs always use WC maps (so the CPU cache isn't used).
This should work. In other words, I think the increased alignment
was just working around coherency problems on atoms that have been
fixed in the intervening 6 year time period.
Untyped surface messages require 4B alignment.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5016
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11727>
Since writers are counted in the accessor set, the old implementation
had a redundant flush in the "flush accessing" case. To fix, split the
two modes into separate functions, removing the redundancy and offering
a much more ergonomic API.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11077>
Squashed together with commits from Boris's original dependency tracking
cleanup series.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11077>
Reduces the work that other shader passes have to do to look at dead code,
and possibly extra rounds around the optimization loop if dce wasn't the
last pass in it.
shader-db runtime -1.12919% +/- 0.264337% (n=49) on SKL.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11628>
Mike Blumenkrantz
Alyssa Rosenzweig
Daniel Stone
Jason Ekstrand
Jason Ekstrand
Kenneth Graunke
Boris Brezillon
Alyssa Rosenzweig
Emma Anholt