Commit Graph

50545 Commits

Author SHA1 Message Date
Francisco Jerez e136453062 gallium: Add pipe loader for device enumeration and driver multiplexing.
The goal is to have a uniform interface to create winsys and
pipe_screen instances for any driver, exposing the device enumeration
capabilities that might be supported by the operating system (for now
there's a "drm" back-end using udev and a "sw" back-end that always
returns the same built-in devices).

The typical use case of this library will be:
>
> struct pipe_loader_device devs[n];
> struct pipe_screen *screen;
>
> pipe_loader_probe(&devs, n);
>[pick some device from the array...]
>
> screen = pipe_loader_create_screen(dev, library_search_path);
>[do something with screen...]
>
> screen->destroy(screen);
> pipe_loader_release(&devs, N);
>

A part of the code was taken from targets/gbm/pipe_loader.c, which
will be removed and replaced with calls into this library by a future
commit.
2012-05-11 12:39:43 +02:00
Francisco Jerez 2faf01c840 gallium/tgsi/text: Replace open-coded integer parsing with parse_int(). 2012-05-11 12:39:43 +02:00
Francisco Jerez 40123dae43 gallium/tgsi/text: Parse immediates of non-float data types. 2012-05-11 12:39:43 +02:00
Francisco Jerez e9072863b1 gallium/tgsi: Fix tgsi_build_full_immediate() for non-float data types. 2012-05-11 12:39:43 +02:00
Francisco Jerez a426b0d5bc gallium/tgsi/text: Make label parsing optional for branch instructions.
Structured branch instructions like IF, ELSE, BGNLOOP, ENDLOOP no
longer require a label argument, make it optional for them.
2012-05-11 12:39:43 +02:00
Francisco Jerez 49468a1b2a st/mesa: Use local temporary registers.
Local makes more sense in most places because non-inline function
calls are unimplemented anyway.
2012-05-11 12:39:42 +02:00
Francisco Jerez b52e374ad3 gallium/tgsi/ureg: Support local temporary emission. 2012-05-11 12:39:42 +02:00
Francisco Jerez 1b8aecc797 gallium/tgsi/ureg: Lift the restriction on releasing temporaries over UREG_MAX_TEMP. 2012-05-11 12:39:42 +02:00
Francisco Jerez 0a62af3bcc gallium/util: Define util_strchrnul.
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2012-05-11 12:39:42 +02:00
Francisco Jerez 57c048f291 gallium/compute: Drop TGSI dependency.
Add a shader cap for specifying the preferred shader representation.
Right now the only supported value is TGSI, other enum values will be
added as they are needed.

This is mainly to accommodate AMD's LLVM compiler back-end by letting
it bypass the TGSI representation for compute programs.  Other drivers
will keep using the common TGSI instruction set.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-05-11 12:39:42 +02:00
Francisco Jerez 2644952bd4 gallium/tgsi: Introduce the "LOCAL" register declaration modifier.
This change will be useful to implement function parameter passing on
top of TGSI.  As we don't have a proper stack, a register-based
calling convention will be used instead, which isn't necessarily a bad
thing given that GPUs often have plenty of registers to spare.

Using the same register space for local temporaries and
inter-procedural communication caused some inefficiencies, because in
some cases the register allocator would lose the freedom to merge
temporary values together into the same physical register, leading to
suboptimal register (and sometimes, as a side effect, instruction)
usage.

The LOCAL declaration modifier specifies that the value isn't intended
for parameter passing and as a result the compiler doesn't have to
give any guarantees of it being preserved across function boundaries.

Ignoring the LOCAL flag doesn't change the semantics of a valid
program in any way, because local variables are just supposed to get a
more relaxed treatment.  IOW, this should be a backwards-compatible
change.
2012-05-11 12:39:41 +02:00
Francisco Jerez c2d31a83a8 gallium/tgsi: Add support for atomic opcodes. 2012-05-11 12:39:41 +02:00
Francisco Jerez 9e550c3423 gallium/tgsi: Add support for barriers. 2012-05-11 12:39:41 +02:00
Francisco Jerez 581ddbcf93 gallium/tgsi: Define system values used to query the compute grid parameters. 2012-05-11 12:39:41 +02:00
Francisco Jerez b8e808f1ef gallium/tgsi: Add resource write-back support.
Define a new STORE opcode with a role dual to the LOAD opcode, and add
flags to specify that a shader resource is intended for writing.
2012-05-11 12:39:41 +02:00
Francisco Jerez 82c90b2da8 gallium/tgsi: Add support for raw resources.
Normal resource access (e.g. the LOAD TGSI opcode) is supposed to
perform a series of conversions to turn the texture data as it's found
in memory into the target data type.

In compute programs it's often the case that we only want to access
the raw bits as they're stored in some buffer object, and any kind of
channel conversion and scaling is harmful or inefficient, especially
in implementations that lack proper hardware support to take care of
it -- in those cases the conversion has to be implemented in software
and it's likely to result in a performance hit even if the pipe_buffer
and declaration data types are set up in a way that would just pass
the data through.

Add a declaration flag that marks a resource as typeless.  No channel
conversion will be performed in that case, and the X coordinate of the
address vector will be interpreted in byte units instead of elements
for obvious reasons.

This is similar to D3D11's ByteAddressBuffer, and will be used to
implement OpenCL's constant arguments.  The remaining four compute
memory spaces can also be understood as raw resources.
2012-05-11 12:39:41 +02:00
Francisco Jerez a4ebb04214 gallium/tgsi: Define the TGSI_BUFFER texture target.
This texture type was already referred to by the documentation but it
was never defined.  Define it as 0 to match the pipe_texture_target
enumeration values.
2012-05-11 12:39:40 +02:00
Francisco Jerez 63428372ca gallium/tgsi: Introduce the compute processor. 2012-05-11 12:39:40 +02:00
Francisco Jerez 1279923d72 gallium/tgsi: Move interpolation info from tgsi_declaration to a separate token.
Move Interpolate, Centroid and CylindricalWrap from tgsi_declaration
to a separate token -- they only make sense for FS inputs and we need
room for other flags in the top-level declaration token.
2012-05-11 12:39:40 +02:00
Francisco Jerez 5f55cbc7d9 gallium: Add context hooks for binding shader resources. 2012-05-11 12:39:40 +02:00
Francisco Jerez a5f44cc8c2 gallium/tgsi: Split sampler views from shader resources.
This commit splits the current concept of resource into "sampler
views" and "shader resources":

"Sampler views" are textures or buffers that are bound to a given
shader stage and can be read from in conjunction with a sampler
object.  They are analogous to OpenGL texture objects or Direct3D
SRVs.

"Shader resources" are textures or buffers that can be read and
written from a shader.  There's no support for floating point
coordinates, address wrap modes or filtering, and, unlike sampler
views, shader resources are global for the whole graphics pipeline.
They are analogous to OpenGL image objects (as in
ARB_shader_image_load_store) or Direct3D UAVs.

Most hardware is likely to implement shader resources and sampler
views as separate objects, so, having the distinction at the API level
simplifies things slightly for the driver.

This patch introduces the SVIEW register file with a declaration token
and syntax analogous to the already existing RES register file.  After
this change, the SAMPLE_* opcodes no longer accept a resource as
input, but rather a SVIEW object.  To preserve the functionality of
reading from a sampler view with integer coordinates, the
SAMPLE_I(_MS) opcodes are introduced which are similar to LOAD(_MS)
but take a SVIEW register instead of a RES register as argument.
2012-05-11 12:39:39 +02:00
Francisco Jerez d9d82dcd00 gallium: Basic compute interface.
Define an interface that exposes the minimal functionality required to
implement some of the popular compute APIs.  This commit adds entry
points to set the grid layout and other state required to keep track
of the usual address spaces employed in compute APIs, to bind a
compute program, and execute it on the device.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-05-11 12:39:39 +02:00
Michel Dänzer c2f1fbf912 radeonsi: Properly translate vertex format swizzle.
egltri_screen works correctly!
2012-05-11 11:54:58 +02:00
Tom Stellard 03d9c24c04 radeon/llvm: Remove AMDILMCCodeEmitter.cpp 2012-05-10 15:54:43 -04:00
Tom Stellard 628e5b208a radeon/llvm: Remove SILowerShaderInstructions.cpp 2012-05-10 15:41:32 -04:00
Tom Stellard f8e9c29020 radeonsi/llvm: Move lowering of RETURN to ConvertToISA pass 2012-05-10 15:41:32 -04:00
Tom Stellard fa63f97652 radeon/llvm: Add some comments 2012-05-10 15:41:31 -04:00
Tom Stellard 92faa21d29 radeon/llvm: Move util functions into AMDGPU namespace 2012-05-10 15:41:31 -04:00
Paul Berry c569182461 i965/hiz: Convert gen{6,7}_hiz.h to gen{6,7}_blorp.h
This patch renames the gen6_hiz.h and gen7_hiz.h files to correspond
to the renames of the corresponding .cpp files (see previous commit).

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-05-10 10:30:01 -07:00
Paul Berry ea1274c9a6 i965/hiz: Convert gen{6,7}_hiz.c to C++
This patch converts the files gen6_hiz.c and gen7_hiz.c to C++, in
preparation for expanding the HiZ code to support arbitrary blits.

The new files are called gen6_blorp.cpp and gen7_blorp.cpp to reflect
the expanded role that this code will serve--"blorp" stands for "BLit
Or Resolve Pass".

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-05-10 10:30:01 -07:00
Paul Berry 20b153b9ca i965/hiz: Make void pointer type casts explicit
Previous to this patch, gen6_hiz.c contained two implicit type casts
from void * to a a non-void pointer type.  This is allowed in C but
not in C++.  This patch makes the type casts explicit, so that
gen6_hiz.c can be converted into a C++ file.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-05-10 10:30:00 -07:00
Paul Berry f28a7d0e77 intel: Work around differences between C and C++ scoping rules.
In C++, if a struct is defined inside another struct, or its name is
first seen inside a struct or function, the struct is nested inside
the namespace of the struct or function it appears in.  In C, all
structs are visible from toplevel.

This patch explicitly moves the decalartions of intel_batchbuffer to
toplevel, so that it does not get nested inside a namespace when
header files are included from C++.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-05-10 10:30:00 -07:00
Paul Berry 434fc8bde4 intel: Add extern "C" declarations to headers
These declarations are necessary to allow C++ code to call C code
without causing unresolved symbols (which would make the driver fail
to load).

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-05-10 10:30:00 -07:00
Tom Stellard b0bb125736 radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_eg 2012-05-10 11:52:00 -04:00
Tom Stellard fa3747ff2c radeon/llvm: Delete all instructions that have been custom lowered 2012-05-10 11:34:32 -04:00
Michel Dänzer 839cbd7853 radeonsi: Set NONE format for unused vertex shader position export slots. 2012-05-10 13:54:39 +02:00
Michel Dänzer 8f45cea81f radeonsi: Eliminate one more magic number for texture image resources. 2012-05-10 13:54:27 +02:00
Michel Dänzer 36d2914a19 radeonsi: Fix vertex buffer resource for stride 0. 2012-05-10 13:54:27 +02:00
Tom Stellard 788fd04dac radeon/llvm: Remove AMDGPUConstants.pm 2012-05-09 12:49:44 -04:00
Tom Stellard c2e081030e radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_const 2012-05-09 12:49:44 -04:00
Tom Stellard d0403cafd4 radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicate 2012-05-09 12:49:44 -04:00
Brian Paul a1c5513c17 svga: implement CEIL opcode translation
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-05-09 10:53:15 -06:00
Christoph Bumiller f7665ca4fc glsl_to_tgsi: use TGSI_OPCODE_CEIL for ir_unop_ceil
The implementation using FLR was buggy, the second negation could
get lost.
2012-05-09 17:13:14 +02:00
Christoph Bumiller 6ae12bac59 gallium/drivers: handle TGSI_OPCODE_CEIL 2012-05-09 17:09:30 +02:00
Kai Wasserbäch 8c98635d4f r600g: Handle TGSI_OPCODE_CEIL (v2)
v2: Enabled CEIL on Cayman too.

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-05-09 09:40:16 -04:00
Dave Airlie 729d914824 gallivm: implement iabs/issg opcode.
Reimplemented by Olivier Galibert <galibert@pobox.com>

Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-09 08:26:55 +01:00
Yuanhan Liu f939776cb2 i965: fix wrong cube/3D texture layout
Fix wrong cube/3D texture layout for the tailing levels whose width or
height is smaller than the align unit.

From 965 B-spec http://intellinuxgraphics.org/VOL_1_graphics_core.pdf at
page 135:
   All of the LOD=0 q-planes are stacked vertically, then below that,
   the LOD=1 qplanes are stacked two-wide, then the LOD=2 qplanes are
   stacked four-wide below that, and so on.

Thus we should always inrease pack_x_nr, which results to the pitch of LODn
may greater than the pitch of LOD0. So we should refactor mt->total_width
when needed.

This would fix the following webgl test case on all gen4 platforms:
  conformance/textures/texture-size-cube-maps.html

NOTE: This is a candidate for stable release branches.

Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2012-05-09 15:13:56 +08:00
Tom Stellard 5aaaa6a426 radeon/llvm: Remove AMDILUtilityFunctions.cpp 2012-05-08 15:47:46 -04:00
Tom Stellard 21ab46eae8 radeon/llvm: Remove some unused functions from AMDILInstrInfo 2012-05-08 15:47:46 -04:00
Tom Stellard f903da7335 radeon/llvm: Add some comments and fix coding style 2012-05-08 15:47:46 -04:00