Commit Graph

146249 Commits

Author SHA1 Message Date
Dylan Baker 57755cad55 docs: add sha256 sum for 21.2.4 release
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13369>
2021-10-14 20:50:11 +00:00
Dylan Baker 8236a7741d docs: add release notes for 21.2.4
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13369>
2021-10-14 20:50:11 +00:00
Eric Engestrom 70df31f5e0 docs: update calendar for 21.3.0-rc1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13368>
2021-10-14 20:51:08 +01:00
Danylo Piliaiev 1c0eb7aa78 ir3/freedreno: account for component in build_tessfactor_base
The burden was put on the caller, which caused:
- Reading of tess levels back in TCS not accounting for component
- Reading patch outputs in TES account for component twice

Fixes vkd3d tests:
- test_tessellation_read_tesslevel
- test_tessellation_primitive_id
- test_line_tessellation_dxbc

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13338>
2021-10-14 17:35:24 +00:00
Emma Anholt f839b9599f loader: Avoid enumerating drm devices just to get an fd's PCI ID.
Cuts 1/3 of the runtime of the VA-API unit tests (which do a separate
pipe-loader init per test) on radeonsi on my system by not faffing around
in sysfs so much.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13324>
2021-10-14 17:09:55 +00:00
Jason Ekstrand b79e978ae4 vulkan/wsi/win32: Delete the wrapper entrypoints
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13352>
2021-10-14 15:44:51 +00:00
Mike Blumenkrantz f769f34680 nir/print: print bindless info as applicable
this is useful to know

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13204>
2021-10-14 15:11:38 +00:00
Jason Ekstrand 116e23e385 vulkan/log: Don't assert on non-client-visible objects
We already have code to deal with non-client-visible objects but we were
asserting if it didn't fall into one of the clearly mappable error
cases.  However, we didn't have a mapping for VK_ERROR_NOT_PERMITTED
which can happen during object creation.  Let's just be sloppy and drop
the assert.  Worst case, the client gets an error with no object.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13341>
2021-10-14 14:23:45 +00:00
Jason Ekstrand 071437d29d vulkan/log: Tweak our handling of a couple error enums
VK_ERROR_INITIALIZATION_FAILED can happen as part of device creation and
isn't really an instance error in that case.
VK_ERROR_EXTENSION_NOT_PRESENT, on the other hand, is always an instance
thing and we should handle it as such.

Fixes: 0cad3beb2a ("vulkan/log: Add common vk_error and vk_errorf helpers")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13341>
2021-10-14 14:23:45 +00:00
Boris Brezillon fd46749234 vulkan: Set unused entrypoints to vk_entrypoint_stub when compiling with MSVC
If we don't do that we hit the assert(entry[i] != NULL) added by commit
6d44b21d4f ("vulkan: Fix weak symbol emulation when compiling with MSVC").

Fixes: 6d44b21d4f ("vulkan: Fix weak symbol emulation when compiling with MSVC")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13355>
2021-10-14 13:56:38 +00:00
Bas Nieuwenhuizen b4aa5a3fdd radv: Fix modifier property query.
radv_get_modifier_flags read the format properties, doesn't write any. Setting
the central format properties based on the drm format properties doesn't make
any sense.

Fixes: 5dee0d9da9 "radv: switch to VK_FORMAT_FEATURE_2_XXX/VkFormatProperties3KHR"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5498
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13357>
2021-10-14 13:29:42 +00:00
Iago Toral Quiroga 8e6f5aab33 v3dv: fix TLB buffer to image copy path for 3D images
Another instance of not taking the Z offset from the right place. We had
not seen this one until now because we typically use the TFU path, where
we also fixed this same issue in commit df1d08533c.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13356>
2021-10-14 11:29:26 +02:00
Boris Brezillon 6d44b21d4f vulkan: Fix weak symbol emulation when compiling with MSVC
Mapping unimplemented entrypoints to a global function pointer variable
initialized to NULL is a bit cumbersome, and actually led to a bug
in the vk_xxx_dispatch_table_from_entrypoints() template: the !override
case didn't have the right check on the source table entries. Instead of
fixing that case, let's simplify the logic by creating a stub function
and making the alternatename pragma point to this stub. This way we get
rid of all those uneeded xxx_Null symbols/variables and simplify the
tests in vk_xxxx_dispatch_table_from_entrypoints().

Cc: mesa-stable
Fixes: 98c622a96e ("vulkan: Update dispatch table gen for Windows")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13348>
2021-10-14 09:09:23 +02:00
Ian Romanick ae99ea6f4d nir/loop_unroll: Always unroll loops that iterate at most once
Two carchase compute shaders (shader-db) and two Fallout 4 fragment
shaders (fossil-db) were helped.  Based on the NIR of the shaders, all
four had structures like

    for (i = 0; i < 1; i++) {
        ...

	for (...) {
            ...
	}
    }

All HSW+ platforms had similar results. (Ice Lake shown)
total loops in shared programs: 6033 -> 6031 (-0.03%)
loops in affected programs: 4 -> 2 (-50.00%)
helped: 2
HURT: 0

All Intel platforms had similar results. (Ice Lake shown)
Instructions in all programs: 143692018 -> 143692006 (-0.0%)
SENDs in all programs: 6947154 -> 6947154 (+0.0%)
Loops in all programs: 38285 -> 38283 (-0.0%)
Cycles in all programs: 8434822225 -> 8434476815 (-0.0%)
Spills in all programs: 191665 -> 191665 (+0.0%)
Fills in all programs: 298822 -> 298822 (+0.0%)

In the presense of loop unrolling like this, the change in cycles is not
accurate.

v2: Rearrange the logic in the if-condition to read a little better.
Suggested by Tim.

Closes: #5089
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13323>
2021-10-13 20:11:13 -07:00
Dave Airlie c4323dc846 brw/nir: remove unused function prototypes.
These got moved into common code a good while ago.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13328>
2021-10-13 22:52:59 +00:00
Anuj Phogat a98ece61e9 anv: Enable tessellation redistribution
This patch adds Tessellation Distribution on top of Geometry
Distribution. Using recommended values based on performance studies
across a range of workloads.

Rework:
- Add comment for new packet bits (Sagar)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
2021-10-13 22:36:54 +00:00
Anuj Phogat 20c0ca75f5 iris: Enable tessellation redistribution
This patch adds Tessellation Distribution on top of Geometry
Distribution. Using recommended values based on performance studies
across a range of workloads.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
2021-10-13 22:36:54 +00:00
Anuj Phogat 867e2e0716 anv: Enable geometry distribution
Using recommended values based on performance studies across a range
of workloads.

Rework:
 * Always enable geometry distribution
 * Set ListCutIndexEnable if primitive restart is enabled
 * Set distribution mode based on TEEnable
 * Add comment explaining the 3DSTATE_VFG bits (Sagar)

v2:
- Emit 3DSTATE_VFG dynamically based on primitive restart (Ken)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
2021-10-13 22:36:54 +00:00
Anuj Phogat efa27572a1 iris: Enable geometry distribution
Using recommended values based on performance studies across a range
of workloads.

Rework:
 * Always enable geometry distribution
 * Set ListCutIndexEnable if primitive restart is enabled
 * Set distribution mode based on TEEnable

v2:
- Flag missing IRIS_DIRTY_VFG bit (Ken)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
2021-10-13 22:36:54 +00:00
Anuj Phogat 1d224e7f14 genxml/gen125: Update 3DSTATE_TE fields
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
2021-10-13 22:36:54 +00:00
Jordan Justen 9a7e54b87f intel/genxml: Update genxml to support tessellation/geometry distribution
Rework:
- Fix 3DSTATE_VFG opcode (Lionel)
- Fix distribution mode values (Sagar)
- Update 3DSTATE_VFG fields (Anuj)

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
2021-10-13 22:36:54 +00:00
Emma Anholt 3eadb03db7 ci/lvp: Skip some slow tests under ASan.
depending on the runner's load, we might see timeouts.  The
subgroupbroadcast one has hit us a couple times this week.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13346>
2021-10-13 21:41:07 +00:00
Alejandro Piñeiro ec51c8774d v3d/clif: add support for dumping GS shader state
The basic vertex+fragment shader state uses the packet
GL_SHADER_STATE, but when geometry shader are involved, the packet
used is GL_SHADER_STATE_INCLUDING_GS.

Without this commit any program using a geometry shader would dump
their shader state (and their shader state record and attribues) as
binaries.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13269>
2021-10-13 21:23:10 +00:00
Alejandro Piñeiro 19894bec1f v3dv/pipeline: don't clone the nir shader at pipeline_state_create_binning
At that point we didn't call all the v3dv lowerings. So the reference
nir shader used to call the v3d compiler could be different.

Note that at that point the nir shader is only available for internal
shaders (like gs multiview).

This specifically affected multiview tests that wrote gl_PointSize, as
the nir shader for the geometry shader were wrongly exposing
per_vertex_point_size as false, as we were basing our check on the
nir_shader_info, and that was gathered calling nir_shader_gather_info
at pipeline_lower_nir.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13325>
2021-10-13 21:01:03 +00:00
Eric Engestrom c7c484d7f4 VERSION: bump to 22.0
I mistakenly bumped it from 21.3 to 21.4, but there is no 4 (:

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13347>
2021-10-13 20:52:19 +01:00
Eric Engestrom 7d9950e924 docs: reset new_features.txt
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2021-10-13 20:29:27 +01:00
Eric Engestrom 91009cbaa8 VERSION: bump to 21.4
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2021-10-13 20:28:29 +01:00
Kenneth Graunke 02435f1294 iris: Require a 4K alignment for extra clear color BOs.
Apparently, we've been requiring a 4K alignment for internally allocated
clear color addresses to work around some unknown issues.  There's a
comment to that effect in iris_resource_create_with_modifiers().

When importing a dmabuf and tacking on an additional clear color BO, we
only required an alignment of 1.  This wasn't a problem for a long time
because all BO allocations were naturally aligned to the 4K page size.

However, once we enabled suballocation, we were able to allocate "BOs"
at 256B granularity, making this no longer 4K aligned.  Increase the
alignment requirement to 4K to match the behavior of our normal
allocations and also our previous behavior.

Fixes Piglit's ext_image_dma_buf_import-intel-modifiers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5482
Fixes: ce2e2296ab ("iris: Suballocate BO using the Gallium pb_slab mechanism")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13326>
2021-10-13 18:46:03 +00:00
Caio Marcelo de Oliveira Filho 94e07058ee intel/compiler: Remove unused `ret` declaration
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13340>
2021-10-13 17:24:29 +00:00
Caio Marcelo de Oliveira Filho bd2cc4b916 intel/compiler: Convert test_eu_compact to use gtest
Be consistent with the other test suites in intel/compiler.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13340>
2021-10-13 17:24:29 +00:00
Mike Blumenkrantz 420e33f551 radv: move alpha_adjust into conditional during vertex input updating
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>
2021-10-13 17:03:26 +00:00
Mike Blumenkrantz 1b8bdecf6e radv: add a mask of bound descriptor buffers for dynamic vertex input
unnecessarily dereferencing the vertex buffer info array here causes a
ton of cpu overhead due to bad cache locality, so just use a mask to
avoid loading X more cachelines into memory unnecessarily

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>
2021-10-13 17:03:26 +00:00
Mike Blumenkrantz eda5634e25 radv: pre-calc "simple" dynamic vertex input values
when the shader pipeline is known to not require any of the more complex
calculations, those calculations can be excluded from the dynamic update
code

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>
2021-10-13 17:03:26 +00:00
Mike Blumenkrantz c335a4d70e radv: dynamically calculate misaligned_mask for dynamic vertex input
this avoids incurring overhead at draw time, instead shifting it to vertex
binding commands

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>
2021-10-13 17:03:26 +00:00
Mike Blumenkrantz 90d9c8dc62 radv: don't use invalid stride for triggering vertex state change
NULL here means this was regular CmdBindVertexBuffers, so the stride
cannot be used

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>
2021-10-13 17:03:26 +00:00
Adam Jackson 27054f737a egl/dri: Enable FP16 for EGL_EXT_platform_device
Why is this not the same code as EGL_MESA_platform_surfaceless.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13182>
2021-10-13 16:36:27 +00:00
Adam Jackson ea038747df dri: Remove the allow_fp16_configs option, always allow them
There's no danger of accidentally using these, the default pixel format
is integer and if you want float you need to have explicitly asked for
it in eglChooseConfig.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13182>
2021-10-13 16:36:27 +00:00
Adam Jackson b01fe97a39 wsi/x11: Fetch and discard the SYNC extension info
Since we're not checking for this, xcb has to do it for us the first
time we call xcb_sync_destroy_fence, which puts a blocking round-trip in
the swapchain destroy path for no reason. Check for the extension so we
have the extension's opcode cached when we need it.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13339>
2021-10-13 16:11:11 +00:00
Lone_Wolf ebfbb42e0e clover: TargetRegistry.h was moved to another folder
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13290>
2021-10-13 15:41:49 +00:00
Emma Anholt cdc009f5aa Revert "ci: Add osmesa to Windows GitLab CI"
This reverts commit 90faabc0ee.  It has been
flaky and producing timeouts.  (See
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/14634204 for an example)

Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13318>
2021-10-13 15:01:52 +00:00
Lionel Landwerlin 9fb2c84768 isl: only bump the min row pitch for display when not specified
If the ISL caller didn't specify a row_pitch_B, let's use the
NVIDIA/AMD requirements. Otherwise keep using the Intel requirement,
as the caller is likely trying to import a buffer and if we can deal
with that row_pitch_B, we should accept it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a3a4517f41 ("isl: Work around NVIDIA and AMD display pitch requirements")
Reported-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13024>
2021-10-13 14:46:49 +00:00
Lionel Landwerlin 47ff6767ea anv: fill correct surface state for lowered storage image
Small typo/copy-paste.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c0093c4668 ("anv: Flip around the way we reason about storage image lowering")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13332>
2021-10-13 14:33:14 +00:00
Bas Nieuwenhuizen fd8210f27e radv: Try to do a better job of dealing with L2 coherent images.
Only try to invalidate L2 if we actually hit one of the incoherent images.

Note we may actually insert some extra flushes at the end of a command
buffer so that we may asume the caches are clean the start of the next
command buffer. However, on average I think that case is uncommon
enough that being able to make assumptions at the start of a cmdbuffer
is beneficial. Especially since MSAA is somewhat rare in more recent
games.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13239>
2021-10-13 14:07:05 +00:00
Bas Nieuwenhuizen 64b237436a radv: Add hooks after in-renderpass meta operations.
So that we can mark the rendertargets dirty.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13239>
2021-10-13 14:07:05 +00:00
Bas Nieuwenhuizen 3de7ba13f5 radv: Document cache coherency rules.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13239>
2021-10-13 14:07:05 +00:00
Hyunjun Ko 30b4911031 turnip: enable strictLines
Now we can enable strictLines as we set rectangular lines by default.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6020>
2021-10-13 12:18:01 +00:00
Hyunjun Ko 542211676c turnip: enable VK_EXT_line_rasterization
By default line mode is VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT,
when lineRasterizationMode is VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
and primtype is line - we enable bresenham line mode.

We have to disable MSAA when bresenham lines are used, this is
a hardware limitation and spec allows it:

  "When Bresenham lines are being rasterized, sample locations may
   all be treated as being at the pixel center (this may affect
   attribute and depth interpolation)."

This forces us to re-emit msaa state when line mode is changed.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6020>
2021-10-13 12:18:01 +00:00
Hyunjun Ko 88afceacf0 freedreno/a5xx,a6xx: rename MSAA_ENABLE to LINE_MODE in GRAS_SU_CNTL
This bit seems like the control for line mode of rastrization.

That can be simply figured out by comparing
dEQP-VK.rasterization.primitives.no_stipple.bresenham_lines,
dEQP-VK.rasterization.primitives.no_stipple.rectangular_lines and
dEQP-VK.rasterization.primitives.no_stipple.lines.

For opengl, the value of bresenham lines mode, which is 0, is set
by default and the value of rectangular mode, which is 0x1, is set
when multi-sampled.

For vulkan, the bresenham lines are enabled when lineRasterizationMode is
VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT, which sets the bit to 0, while
the value is 1 when it's VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT,
that seems to be default.

If both multi-sampled and bresenham-lines are used when primitive type is
line, the bit is to be set as 0 and makes msaa disabled.

Note that this is only tested on a6xx, but I guess it's likely the same
for a5xx.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6020>
2021-10-13 12:18:01 +00:00
Tapani Pälli d729038c07 anv: use vk_object_zalloc for wsi fences created
Otherwise we hit assert in vk_object_base_assert_valid when attemping to
create handle from anv_fence with unknown base type.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13330>
2021-10-13 11:59:17 +00:00
Emma Anholt 4721352f97 radeonsi: Fix leak of screen->perfcounters.
A refactor dropped one of the frees.

Fixes: 380ac28891 ("ac: import performance counters from RadeonSI")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13322>
2021-10-13 11:01:19 +00:00