iris: Enable geometry distribution
Using recommended values based on performance studies across a range of workloads. Rework: * Always enable geometry distribution * Set ListCutIndexEnable if primitive restart is enabled * Set distribution mode based on TEEnable v2: - Flag missing IRIS_DIRTY_VFG bit (Ken) Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
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@ -115,6 +115,7 @@ enum {
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#define IRIS_DIRTY_VERTEX_BUFFER_FLUSHES (1ull << 32)
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#define IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES (1ull << 33)
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#define IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES (1ull << 34)
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#define IRIS_DIRTY_VFG (1ull << 35)
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#define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES | \
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IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES)
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@ -65,6 +65,7 @@ iris_update_draw_info(struct iris_context *ice,
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const struct pipe_draw_info *info)
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{
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struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
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const struct intel_device_info *devinfo = &screen->devinfo;
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const struct brw_compiler *compiler = screen->compiler;
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if (ice->state.prim_mode != info->mode) {
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@ -105,8 +106,11 @@ iris_update_draw_info(struct iris_context *ice,
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if (ice->state.primitive_restart != info->primitive_restart ||
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ice->state.cut_index != cut_index) {
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ice->state.dirty |= IRIS_DIRTY_VF;
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ice->state.primitive_restart = info->primitive_restart;
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ice->state.cut_index = cut_index;
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ice->state.dirty |=
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((ice->state.primitive_restart != info->primitive_restart) &&
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devinfo->verx10 >= 125) ? IRIS_DIRTY_VFG : 0;
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ice->state.primitive_restart = info->primitive_restart;
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}
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}
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@ -2844,10 +2844,13 @@ static void
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iris_bind_tes_state(struct pipe_context *ctx, void *state)
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{
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struct iris_context *ice = (struct iris_context *)ctx;
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struct iris_screen *screen = (struct iris_screen *) ctx->screen;
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const struct intel_device_info *devinfo = &screen->devinfo;
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/* Enabling/disabling optional stages requires a URB reconfiguration. */
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if (!!state != !!ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL])
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ice->state.dirty |= IRIS_DIRTY_URB;
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ice->state.dirty |= IRIS_DIRTY_URB | (devinfo->verx10 >= 125 ?
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IRIS_DIRTY_VFG : 0);
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bind_shader_state((void *) ctx, state, MESA_SHADER_TESS_EVAL);
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}
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@ -6586,6 +6586,9 @@ iris_upload_dirty_render_state(struct iris_context *ice,
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if (dirty & IRIS_DIRTY_VF) {
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iris_emit_cmd(batch, GENX(3DSTATE_VF), vf) {
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#if GFX_VERx10 >= 125
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vf.GeometryDistributionEnable = true;
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#endif
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if (draw->primitive_restart) {
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vf.IndexedDrawCutIndexEnable = true;
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vf.CutIndex = draw->restart_index;
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@ -6593,6 +6596,33 @@ iris_upload_dirty_render_state(struct iris_context *ice,
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}
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}
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#if GFX_VERx10 >= 125
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if (dirty & IRIS_DIRTY_VFG) {
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iris_emit_cmd(batch, GENX(3DSTATE_VFG), vfg) {
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/* If 3DSTATE_TE: TE Enable == 1 then RR_STRICT else RR_FREE*/
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vfg.DistributionMode =
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ice->shaders.prog[MESA_SHADER_TESS_EVAL] != NULL ? RR_STRICT :
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RR_FREE;
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vfg.DistributionGranularity = BatchLevelGranularity;
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vfg.ListCutIndexEnable = draw->primitive_restart;
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/* 192 vertices for TRILIST_ADJ */
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vfg.ListNBatchSizeScale = 0;
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/* Batch size of 384 vertices */
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vfg.List3BatchSizeScale = 2;
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/* Batch size of 128 vertices */
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vfg.List2BatchSizeScale = 1;
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/* Batch size of 128 vertices */
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vfg.List1BatchSizeScale = 2;
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/* Batch size of 256 vertices for STRIP topologies */
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vfg.StripBatchSizeScale = 3;
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/* 192 control points for PATCHLIST_3 */
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vfg.PatchBatchSizeScale = 1;
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/* 192 control points for PATCHLIST_3 */
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vfg.PatchBatchSizeMultiplier = 31;
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}
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}
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#endif
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if (dirty & IRIS_DIRTY_VF_STATISTICS) {
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iris_emit_cmd(batch, GENX(3DSTATE_VF_STATISTICS), vf) {
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vf.StatisticsEnable = true;
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