Commit Graph

8 Commits

Author SHA1 Message Date
Danylo Piliaiev 4218596671 ir3/freedreno: handle non-uniform a1en instructions
Fixes vkd3d test "test_bindless_samplers_sm51"

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13311>
2021-10-12 17:43:52 +00:00
Christian Gmeiner dbb9d3d0e3 freedreno/isa: encode: switch bitmask_t to BITSET_WORD's
This commit changes the underlying basetype of bitmask_t to a
BITSET_WORD based one.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11321>
2021-09-21 20:25:31 +00:00
Rob Clark cc72eeb077 freedreno/ir3: Reduce use of compiler->gpu_id
For the same reason as previous patch.  Mostly we only care about the
generation, so convert things to use compiler->gen instead.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12159>
2021-08-06 18:51:50 +00:00
Danylo Piliaiev 1c6c200c0d ir3: add newly found shlg.b16 instruction
Example of blob's output:
  (nop3) shlg.b16 hr8.x, (r)8, (r)hr8.x, 12

It does: (src2 << src1) | src2

src1 and src2 could be GPRs, relative GPRs, relative consts,
or immidiates. However, they could not be plain const registers.

Blob does use it in conjuncture with "samgq" instruction.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11760>
2021-07-09 13:00:29 +00:00
Connor Abbott bff83fc42b freedreno/isa: Convert to srcs/dsts
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Danylo Piliaiev 9dd9424a85 turnip: implement VK_EXT_shader_demote_to_helper_invocation
The "demote" intrinsic has the semantics of D3D discard, which means
it doesn't change the control flow, allowing derivatives to work.

On A6xx there is no known way to check whether invocation was demoted,
thus we use nir_lower_is_helper_invocation.

Add "logical" OPC_DEMOTE which is later translated to "kill".
Such separation is necessary to run "kill" specific optimizations
which are invalid for "demote".

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9460>
2021-04-19 17:11:36 +00:00
Hyunjun Ko e9fd2a2a58 ir3: Add nonuniform encodings to ir3 encoder and parser
By keeping track of nonuniform access from nir and storing it to ir3.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9125>
2021-03-17 01:09:30 +00:00
Rob Clark e7630ec278 freedreno/hw: Add isaspec mechanism for documenting/defining an ISA
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
2021-01-13 18:32:47 +00:00