Commit Graph

112109 Commits

Author SHA1 Message Date
Thomas Hellstrom 3b828c4e68 svga: Map vertex- index- and constant buffers ansynchronously when reading
With SWTNL and index translation we're mapping buffers for reading. These
buffers are commonly upload_mgr buffers that might already be referenced
by another submitted or unsubmitted GPU command. A synchronous map will
then trigger a flush and sync, at least on Linux that doesn't distinguish
between read- and write referencing. So map these buffers async. If they
for some obscure reason happen to be dirty (stream-output, buffer-copy),
the resource_buffer code will read-back and sync anyway. For persistent /
coherent buffers a corresponding read-back and sync will happen in the
kernel fault handler.

Testing: Piglit quick. No regressions.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2019-06-20 09:30:22 +02:00
Thomas Hellstrom f51915ba62 svga: Fix index buffer uploads
In the case of SWTNL and index translation we were uploading index buffers
and then reading out from them using the CPU. Furthermore, when translating
indices we often cached the results with an upload_mgr buffer, causing the
cached indexes to be immediately discarded on the next write to that
upload_mgr buffer.

Fix this by only uploading when we know the index buffer is going to be
used by hardware. If translating, only cache translated indices if the
original buffer was not a user buffer. In the latter case when we're not
caching, use an upload_mgr buffer for the hardware indices.

This means we can also remove the SWTNL hand-crafted index buffer upload
mechanism in favour of the upload_mgr.

Finally avoid using util_upload_index_buffer(). It wastes index buffer
space by trying to make sure that the offset of the indices in the
upload_mgr buffer is larger or equal to the position of the indices in
the source buffer. From what I can tell, the SVGA device does not
require that.

Testing done: Piglit quick. No regressions.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2019-06-20 09:30:22 +02:00
Thomas Hellstrom 4f59d51d82 winsys/svga: Make it possible to specify coherent resources
Add a flag in the surface cache key and a winsys usage flag to
specify coherent memory.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2019-06-20 09:30:22 +02:00
Thomas Hellstrom 4412be40dd gallium/util: Make u_debug_flush support persistent maps
Previously unsynchronized maps have been assumed to also be persistent,
Now destinguish between persistent and unsynchronized map and also support
PIPE_TRANSFER_PERSISTENT from ARB_buffer_storage.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2019-06-20 09:30:22 +02:00
Gert Wollny a478e56fbd virgl: Add debug flag to bypass driconf to enable the BGRA tweaks
This useful for testing, also because with vtest the dri configuration
is not read.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-06-20 08:50:38 +02:00
Gert Wollny 5dbecf7863 virgl: Add a tweak to set the value for emulated queries of GL_SAMPLES_PASSED
On GLES hosts GL_SAMPLES_PASSED is emulated by GL_ANY_SAMPLES_PASSED which returns a boolen.
With this tweak the value that is returned if any sample passed can be set. This
may be of iterest when an application decides whether some geometry is rendered based
on an amount of visibility and not just a binary desicion. virgelrenderer sets a default
of 1024 on th host.

v2: Remove reference from virgl and correct description (Emil)
v3: Send the tweak binary encoded instead of using strings (Gurchetan)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-06-20 08:50:38 +02:00
Gert Wollny 59757dbad6 virgl: Add tweak to apply a swizzle when drawing/blitting to a emulated BGRA texture
With Qemu this final swizzle is not needed, but with vtest it is, i.e. it depends on
how a program using virglrenderer uses the surface that is rendered to, hence
a tweak is added.

v2: Update description and fix spelling (Emil)
v3: Send tweak as binary value instead of using strings (Gurchetan)
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-06-20 08:50:38 +02:00
Gert Wollny b793663449 virgl: Add driconf tweak for emulating BGRA surfaces on GLES
These tweaks are used to fix rendering issues with Valve games and
at least also "The Raven Remastered" when run on a GLES host.

v2: Fix type in define and remove virgl from driconf option (Emil)
v3: Encode tweak binary instead of using strings (Gurchetan)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-06-20 08:50:38 +02:00
Gert Wollny 13d4a34c44 virgl: Add override for BGRA format to use swizzled SRGB format
Tie in the check whether the host supports tweaks and whether this tweak
is enabled.

v2: Add comment about the emulated formats not being used directly in the
    guest (Gurchetan)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-06-20 08:50:38 +02:00
Gert Wollny 22edafb239 virgl: Add code to accept BGRx_SRGB as RGBx_SRGB
This will be enabled in later patches by the emulation tweak.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-06-20 08:50:38 +02:00
Gert Wollny d8967b7951 virgl: Add skeleton to evaluate cap and send tweaks
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-06-20 08:50:38 +02:00
Gert Wollny 28dc096e15 virgl: factor out format host bits check
This will make it a single location when we want to replace a format.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-06-20 08:50:38 +02:00
Gert Wollny 30eb1fdc51 gallium/virgl: Add code path for virgl to read driconf
This works only for the drm variant of virgl and not for the vtest
variant.

v2: Rebase, replace the configuration query function by a pointer to
    the configuration data.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (v1)
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-06-20 08:50:38 +02:00
Gert Wollny cf800998af virgl: Add driinfo file and tie it into the build
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-06-20 08:50:37 +02:00
Caio Marcelo de Oliveira Filho 9b0720c436 glspirv: Call pass to lower frexp instructions
These were previously handled by the spirv_to_nir, but that changed to
be an explict pass in 23d30f4099 "spirv,nir: lower
frexp_exp/frexp_sig inside a new NIR pass"

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-06-19 22:07:57 -07:00
Caio Marcelo de Oliveira Filho 12131096fa spirv: Restrict use of descriptor intrinsics to Vulkan
In ARB_gl_spirv we'll be able to use variables for uniform buffers, so
don't use the descriptor intrinsics to lower the block access.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-06-19 22:07:51 -07:00
Nicolai Hähnle 21dd881416 ac/rtld: report better error messages for LDS overallocation
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2019-06-19 20:30:32 -04:00
Marek Olšák b64bd5887e ac/rtld: check correct LDS max size
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2019-06-19 20:30:32 -04:00
Nicolai Hähnle 1ee0f0d315 radeonsi: add s_sethalt to shaders for debugging
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2019-06-19 20:30:32 -04:00
Nicolai Hähnle 87182200c7 ac/rtld: fix sorting of LDS symbols by alignment
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2019-06-19 20:30:32 -04:00
Bas Nieuwenhuizen d1c04835ab meson: Allow building radeonsi with just the android platform.
Just as was allowed by autotools.

Fixes: 108d257a16 "meson: build libEGL"
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-06-19 23:42:49 +00:00
Bas Nieuwenhuizen 755c633b8d anv: Fix vulkan build in meson.
Apparently the android part was never ported to meson.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-06-19 23:27:46 +00:00
Bas Nieuwenhuizen 4c300bd328 radv: Fix vulkan build in meson.
Apparently the android part was never ported to meson.

CC: <mesa-stable@lists.freedesktop.org>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-06-19 23:27:46 +00:00
Jason Ekstrand ef323d02d8 anv/image: Set different usage flags for shadow surfaces
For the block BLOCK_TEXEL_VIEW_COMPATIBLE case, this didn't matter
because the flags were already more-or-less what we wanted.  However,
for gen7 stencil shadow images, it still had ISL_SURF_USAGE_STENCIL_BIT
so we were getting W-tiled which isn't what we want for the shadow.  By
passing just ISL_SURF_USAGE_TEXTURE_BIT (and CUBE if we care), we now
get something that's actually texturable.

Fixes: f3ea0cf828 "anv: Add stencil texturing support for gen7"
2019-06-19 22:21:46 +00:00
Jason Ekstrand 215f9f83f5 anv: Flush caches in anv_image_copy_to_shadow
Copies to a shadow image happen during a VkCmdPipelineBarrier or at
subpass transitions.  We could potentially be a bit more conservative
but these transitions shouldn't happen often and it's better to have our
bases covered.

Fixes: f3ea0cf828 "anv: Add stencil texturing support for gen7"
2019-06-19 22:21:46 +00:00
Jason Ekstrand 81e51b412e nir: Make nir_constant a vector rather than a matrix
Most places in NIR, we treat matrices like arrays.  The one annoying
exception to this has been nir_constant where a matrix is a first-class
thing.  This commit changes that so a matrix nir_constant is the same as
an array nir_constant.  This makes matrix nir_constants a tiny bit more
expensive but shrinks all others by 96B.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-06-19 21:05:54 +00:00
Jason Ekstrand b019fe8a5b glsl/nir: Fix handling of 64-bit values in uniform storage
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-06-19 21:05:54 +00:00
Jason Ekstrand a54e397152 spirv: Only copy needed components for OpSpecConstantOp
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-06-19 21:05:54 +00:00
Jason Ekstrand 96bb9c9277 spirv: Use a single path for OpSpecConstantOp of OpVectorShuffle
Now that nir_const_value is a scalar, there's no reason why we need
multiple paths here and it's just extra paths to keep working.  While
we're here, we also add a vtn_fail_if check that component indices are
in-bounds.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-06-19 21:05:54 +00:00
Jason Ekstrand 280e5442e5 spirv: Use vtn_constan_uint() for array lengths and gather components
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-06-19 21:05:54 +00:00
Jason Ekstrand aa11c2e75e spirv: Add a vtn_constant_int helper
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-06-19 21:05:54 +00:00
Jason Ekstrand 93f4aa9889 glsl/types: Add a real is_integer helper
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-06-19 20:28:52 +00:00
Jason Ekstrand f0920e266c glsl/types: Rename is_integer to is_integer_32
It only accepts 32-bit integers so it should have a more descriptive
name.  This patch should not be a functional change.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-06-19 20:28:52 +00:00
Jason Ekstrand 21a7e6d569 glsl/types: Ignore bit sizes in contains_integer()
All of the callers for this function are looking at interpolation
qualifiers and want to make sure they're declared flat.  Any 64-bit
integer inputs need to be flat.  It's also makes the function make more
sense since "integer" is fairly generic.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-06-19 20:28:52 +00:00
Jason Ekstrand 0d1fb380b1 glsl/types: Handle all bit sizes in glsl_type_is_integer
All of the callers of this function really just want to know if the type
is an integer and don't care about bit size.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-06-19 20:28:52 +00:00
Caio Marcelo de Oliveira Filho feb0cdcb52 glsl/nir_opt_access: Update uniforms correctly when only vars change
Even if only variables access flags are changed, the existing NIR
infrastructure expects metadata to be explicitly preserved, so do
that.  Don't care about avoiding preserve to be called twice since the
cost is negligible.

This scenario can be triggered by dead variables, and also by other
intrinsics that read the variables -- but not cause progress to be
made when processing the intrinsics.

Fixes: f2d0e48ddc "glsl/nir: Add optimization pass for access flags"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-06-19 12:50:41 -07:00
Caio Marcelo de Oliveira Filho d7ea433a5f glsl/nir: Fix getting the sampler dim when arrays are involved
Unwrap any array in the variable type so we can get the sampler dim.

This fixes piglit test
spec/arb_arrays_of_arrays/execution/image_store/basic-imageStore-const-uniform-index.shader_test.

Fixes: f2d0e48ddc "glsl/nir: Add optimization pass for access flags"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-06-19 12:50:39 -07:00
Jory Pratt 10e8d46601 meson: Search for execinfo.h
Rather than checking __GLIBC__/__UCLIBC__ macros as a proxy for
execinfo.h presence, just check directly. This allows the build to work
on musl.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-06-19 12:16:18 -07:00
Jory Pratt fd7b7f14d8 util: Heap-allocate 256K zlib buffer
The disk cache code tries to allocate a 256 Kbyte buffer on the stack.
Since musl only gives 80 Kbyte of stack space per thread, this causes a
trap.

See https://wiki.musl-libc.org/functional-differences-from-glibc.html#Thread-stack-size

(In musl-1.1.21 the default stack size has increased to 128K)

[mattst88]: Original author unknown, but I think this is small enough
            that it is not copyrightable.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-06-19 12:16:18 -07:00
Kenneth Graunke 9c19d07b1c anv: Fix wrong printf formatter
%lu is for unsigned long, %zu is for size_t.  Just cast the data.
2019-06-19 11:57:01 -05:00
Kenneth Graunke bbbf7a538c iris: Bail on queries for INTEL_NO_HW=1.
We don't execute any of the commands to record snapshots, so we can't
actually produce a real result.  We do however need to avoid waiting
on a syncpt which will never be signalled.  So, just return 0.
2019-06-19 11:55:43 -05:00
David Riley 11e74daae5 virgl: Support VIRGL_BIND_SHARED
Support a new virgl bind type for shared buffers.

Signed-off-by: David Riley <davidriley@chormium.org>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
2019-06-19 07:28:47 -07:00
Lionel Landwerlin bc62673dce anv: write spirv-nir logs back to the application
Using the existing VK_EXT_debug_report extension.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-06-19 15:45:52 +03:00
Connor Abbott 53a7649e5d ac/nir: Set speculatable for buffer loads where allowed
This brings the nir path in line with the TGSI path.

Totals from affected shaders:
SGPRS: 2984 -> 2984 (0.00 %)
VGPRS: 2792 -> 2652 (-5.01 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 247380 -> 248072 (0.28 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 121 -> 132 (9.09 %)
Wait states: 0 -> 0 (0.00 %)

Most of the change came from DiRT: Showdown, and came from sinking SSBO
loads.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-06-19 14:08:28 +02:00
Connor Abbott 77be5b2f88 nir: Use reorderable access flag
No changes with radeonsi shader-db.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-06-19 14:08:28 +02:00
Connor Abbott a1c737927c nir: Add a helper to determine if an intrinsic can be reordered
This is simple now, but we're going to be adding a few more conditions
to this later.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-06-19 14:08:28 +02:00
Connor Abbott 6fc83c253f st/nir: Use gl_nir_opt_access
Nothing uses its results yet, that will come with the following commits.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-06-19 14:08:28 +02:00
Connor Abbott f2d0e48ddc glsl/nir: Add optimization pass for access flags
Right now, this just deduces when we can arbitrarily reorder SSBO and
image loads, matching the existing logic in radeonsi's TGSI->LLVM pass.
This approach can't handle some things that nir_opt_copy_prop_vars can,
but it can handle images, and with GCM it lets us hoist reads outside of
loops. We can also pass this information to LLVM which lets it do its
own optimizations on it.

This is GLSL only as I haven't tested it on Vulkan yet, and it would
probably need a few changes to work there.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-06-19 14:08:28 +02:00
Connor Abbott c813c5776d nir: Add reorderable memory access enum
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-06-19 14:08:28 +02:00
Connor Abbott 75063fbac5 nir/copy_prop_vars: Ignore volatile accesses
The spec explicitly says that volatile writes can't be removed and
volatile reads do not guarantee that the same value will still be around
after the read, as if there were a barrier after each read/write. Just
ignore them.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-06-19 14:08:28 +02:00