Commit Graph

50649 Commits

Author SHA1 Message Date
Vadim Girlin d6aa7cd7f8 radeon/llvm: add suport for cube textures
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:23 +04:00
Vadim Girlin e98e209528 radeon/llvm: add support for CUBE ALU instruction
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:23 +04:00
Vadim Girlin 996fa375ec radeon/llvm: add support for some ALU instructions
Add support for IABS, NOT, AND, XOR, OR, UADD, UDIV, IDIV, MOD, UMOD, INEG,
I2F, U2F, F2U, F2I, USEQ, USGE, USLT, USNE, ISGE, ISLT, ROUND, MIN, MAX,
IMIN, IMAX, UMIN, UMAX

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:23 +04:00
Vadim Girlin e9be193430 radeon/llvm: add missing cases for BREAK/CONTINUE
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin e740b60845 radeon/llvm: add support for AHSR/LSHR/LSHL instructions
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin 95ed0e9b6b radeon/llvm: add support for TXQ/TXF/DDX/DDY instructions
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin d8a1204854 radeon/llvm: add support for VertexID, InstanceID
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin e3e7ae732c radeon/llvm: fix live-in handling for inputs
Set the input registers as live-in for entry basic block.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin 757f471ba9 radeon/llvm: add support for v4i32
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin 06db74a753 radeon/llvm: fix ABS_i32 instruction lowering
Swap source operands.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin 3a6a1cd75f radeon/llvm: use integer comparison for IF
Replacing "float equal to 1.0f" with "int not equal to 0".
This should help for further optimization of boolean computations.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin 2a88dfc521 radeon/llvm: use bitcasts for integers
We're using float as default type, so basically for every instruction that
wants other types for dst/src operands we need to perform the bitcast
to/from default float. Currently bitcast produces no-op MOV instruction,
will be eliminated later.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:21 +04:00
Tom Stellard 3f8c37967a r600g: Fix out of tree builds that use the LLVM backend
https://bugs.freedesktop.org/show_bug.cgi?id=49567
2012-05-07 15:05:25 -04:00
Tom Stellard c425c3823f radeon/llvm: Remove references to DebugFlag and isCurrentDebugType()
These weren't being used at all and they were causing build failures
when LLVM was built with NDEBUG defined and mesa was not.

https://bugs.freedesktop.org/show_bug.cgi?id=49110
2012-05-07 14:01:53 -04:00
Paul Berry 714b4f6184 i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets.
In i965 Gen7, Mesa has for a long time used the "depth coordinate
offset X/Y" settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to
render to miplevels other than 0.  Unfortunately, this doesn't work,
because these offsets must be aligned to multiples of 8, and miplevels
in the depth buffer are only guaranteed to be aligned to multiples of
4.  When the offsets aren't aligned to a multiple of 8, the GPU
sometimes hangs.

As a temporary measure, to avoid GPU hangs, this patch smashes the 3
LSB's of "depth coordinate offset X/Y" to 0.  This results in
incorrect rendering to mipmapped depth textures, but that seems like a
reasonable stopgap while we figure out a better solution.

Avoids GPU hangs in piglit test "depthstencil-render-miplevels" at
texture sizes that are not powers of 2.

Reviewed-by: Chad Verace <chad.versace@linux.intel.com>
2012-05-07 10:50:33 -07:00
Paul Berry a683012a80 i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets.
In i965 Gen6, Mesa has for a long time used the "depth coordinate
offset X/Y" settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to
render to miplevels other than 0.  Unfortunately, this doesn't work,
because these offsets must be aligned to multiples of 8, and miplevels
in the depth buffer are only guaranteed to be aligned to multiples of
4.  When the offsets aren't aligned to a multiple of 8, the GPU
sometimes hangs.

As a temporary measure, to avoid GPU hangs, this patch smashes the 3
LSB's of "depth coordinate offset X/Y" to 0.  This results in
incorrect rendering to mipmapped depth textures, but that seems like a
reasonable stopgap while we figure out a better solution.

(Note that we have only ever observed this GPU hang on Gen6 when HiZ
is enabled, so another possible stopgap would be to disable HiZ).

Avoids GPU hangs in piglit test "depthstencil-render-miplevels" at
texture sizes that are not powers of 2.

Reviewed-by: Chad Verace <chad.versace@linux.intel.com>
2012-05-07 10:50:04 -07:00
Paul Berry b9819a027d fbo: Only reuse depth/stencil attachments if the parameters match.
When the user attaches a texture to one of the depth/stencil
attachment points (GL_STENCIL_ATTACHMENT or GL_DEPTH_ATTACHMENT), we
check to see if the same texture is also attached to the other
attachment point, and if so, we re-use the existing texture
attachment.  This is necessary to ensure that if the user later
queries what is attached to GL_DEPTH_STENCIL_ATTACHMENT, they will not
receive an error.

If, however, the user attaches buffers to the two different attachment
points using different parameters (e.g. a different miplevel), then we
can't re-use the existing texture attachment, because it is pointing
to the wrong part of the texture.  This might occur as a transitory
condition if, for example, if the user attached miplevel zero of a
texture to GL_STENCIL_ATTACHMENT and GL_DEPTH_ATTACHMENT, rendered to
it, and then later attempted to attach miplevel one of the same
texture to GL_STENCIL_ATTACHMENT and GL_DEPTH_ATTACHMENT.

This patch causes Mesa to check that GL_STENCIL_ATTACHMENT and
GL_DEPTH_ATTACHMENT use the same attachment parameters before
attempting to share the texture attachment.

On i965 Gen6, fixes piglit tests
"texturing/depthstencil-render-miplevels 1024 depth_stencil_shared"
and "texturing/depthstencil-render-miplevels 1024
stencil_depth_shared".

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-05-07 10:48:53 -07:00
Paul Berry 3ec0e55b63 i965: Fix mipmap offsets for HiZ and separate stencil buffers.
When rendering to a miplevel other than 0 within a color, depth,
stencil, or HiZ buffer, we need to tell the GPU to render to an offset
within the buffer, so that the data is written into the correct
miplevel.  We do this using a coarse offset (in pages), and a fine
adjustment (the so-called "tile_x" and "tile_y" values, which are
measured in pixels).

We have always computed the coarse offset and fine adjustment using
intel_renderbuffer_tile_offsets() function.  This worked fine for
color and combined depth/stencil buffers, but failed to work properly
when HiZ and separate stencil were in use.  It failed to work because
there is only one set of fine adjustment controls shared by the HiZ,
depth, and stencil buffers, so we need to choose tile_x and tile_y
values that are compatible with the tiling of all three buffers, and
then compute separate coarse offsets for each buffer.

This patch fixes the HiZ and separate stencil case by replacing the
call to intel_renderbuffer_tile_offsets() with calls to two functions:
intel_region_get_tile_masks(), which determines how much of the
adjustment can be performed using offsets and how much can be
performed using tile_x and tile_y, and
intel_region_get_aligned_offset(), which computes the coarse offset.

intel_region_get_tile_offsets() is still used for color renderbuffers,
so to avoid code duplication, I've re-worked it to use
intel_region_get_tile_masks() and intel_region_get_aligned_offset().

On i965 Gen6, fixes piglit tests
"texturing/depthstencil-render-miplevels 1024 X" where X is one of
(depth, depth_and_stencil, depth_stencil_single_binding, depth_x,
depth_x_and_stencil, stencil, stencil_and_depth, stencil_and_depth_x).

On i965 Gen7, the variants of
"texturing/depthstencil-render-miplevels" that contain a stencil
buffer still fail, due to another problem: Gen7 seems to ignore the 3
LSB's of the tile_y adjustment (and possibly also tile_x).

v2: Removed spurious comments.  Added assertions to check
preconditions of intel_region_get_aligned_offset().

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-05-07 10:47:49 -07:00
Chad Versace 1c0f5d8324 intel: Disable ARB_framebuffer_object in ES contexts
This patch removes ARB_framebuffer_object from the GLES1 and GLES2
extension lists in intel_extensions_es.c.

Fixes a crash in the Android browser on Ice Cream Sandwich.

The Android browser crashed because it did the following, which is legal
in GLES2 but not in ARB_framebuffer_object.
    glGenFramebuffers(1, &fb);
    glBindFramebuffer(GL_FRAMEBUFFER, fb);
    // render render render...
    glDeleteFramebuffers(1, &fb);
    // go do other stuff...
    glBindFramebuffer(GL_FRAMEBUFFER, fb);
    // This bind unexpectedly failed, and the app panics.

The semantics of glBindFramebuffer specified by ARB_framebuffer_object (a
desktop GL extension) and GLES2 specs are incompatible. The ideal solution
to fix this is to create separate API entry points for glBindFramebuffer,
one for GL and the other for GLES2. But, until that work is complete,
disabling ARB_framebuffer_object in GLES2 contexts safely fixes the problem.

Likewise, the semantics of glBindFramebuffer in ARB_framebuffer_object and
of glBindFramebufferOES in OES_framebuffer_object (a GLES1 extension) are
incompatible. Even though the functions have different names, the semantic
difference still results in a bug because both API calls are implemented
by a single function, _mesa_BindFramebufferEXT, which handles the semantic
difference incorrectly. Again, disabling ARB_framebuffer_object in GLES1
contexts safely fixes this problem.

According to the ARB_framebuffer_object spec, the extension is an
amalgamation of
    EXT_framebuffer_object
    EXT_framebuffer_blit
    EXT_packed_depth_stencil
    EXT_framebuffer_multisample
By disabling this extension, however, no functionality is removed from
GLES1 and GLES2 contexts because 1) the first three extensions are
explicitly enabled in Intel's ES extension lists and 2) no functionality
of the last extension is exposed in an ES context.

Note: This is a candidate for the 8.0 branch.
See-also: http://www.mail-archive.com/mesa-dev@lists.freedesktop.org/msg21006.html
CC: Charles Johnson <charles.f.johnson@intel.com>
CC: Sean Kelley <sean.v.kelley@intel.com>
Reviewed-by: Ian Romanick <idr@freedesktop.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2012-05-07 08:38:12 -07:00
Brian Paul 64c510bb72 mesa: bump version to 8.1.0 in configs/default 2012-05-07 07:30:04 -06:00
Marcin Slusarz ecc7e5e85b nv50: handle VP without inputs 2012-05-07 14:05:35 +02:00
Christoph Bumiller c19672f90a nvc0/ir: allow abs,neg source modifiers with ceil,floor,trunc 2012-05-06 22:03:06 +02:00
Christoph Bumiller 28d6a268af nv50/ir/opt: don't lose saturation in tryCollapseChainedMULs 2012-05-06 22:03:06 +02:00
Christoph Bumiller 38a20281fc nvc0/ir: fix lowering of textureGrad 2012-05-06 22:03:06 +02:00
Christoph Bumiller 9dfac63ae0 nouveau: fix nouveau_scratch_runout_release bo count underflow 2012-05-06 22:03:06 +02:00
Jordan Justen 5795d3b5ae mesa: Add primitive restart support to glArrayElement
When primitive restart is enabled, and glArrayElement is called
with the restart index value, then call glPrimitiveRestartNV.

NOTE: This is a candidate for the 8.0 branch.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul<brianp@vmware.com>
2012-05-05 20:35:08 -07:00
Baldo Davide 0ad0bc5af5 auxiliary/os: Add missing signal.h include.
The signal.h include was missed in the commit
bc16c73407 which leads to broken
compilations under Linux.

Signed-off-by: José Fonseca <jose.r.fonseca@gmail.com>
2012-05-05 04:51:32 +01:00
Kenneth Graunke 3cd7bee48f intel: Remove pointless software fallback for glBitmap on Gen6.
We already have a meta path below that works just fine; no apparent
regressions in oglconform.

NOTE: This is a candidate for the 8.0 branch.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46834
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-05-04 17:19:43 -07:00
Eric Anholt 4595288ba8 glsl: Fix regression in function out-parameter lvalue detection.
When doing the var->assigned change in
f2475ca424, I overzealously indented the
second block of code into the "if (var)" test.  Revert these blocks to
the way they were before, just taking advantage of "var" to avoid
re-calling variable_referenced().

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49066
2012-05-04 14:00:32 -07:00
Eric Anholt 3362c7d9b6 mesa: Prevent buffer underrun when handling MESA_GL_EXTENSION_OVERRIDE. 2012-05-04 14:00:32 -07:00
Eric Anholt dc42910e98 i965/fs: Fix regression in comparison handling from ANDs change.
I had fixed up the logic ops for delayed ANDing, but not equality
comparisons on bools.  Fixes new piglit fs-bool-less-compare-true.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48629
2012-05-04 14:00:32 -07:00
Eric Anholt b2ee5a08ba glsl: Don't consider unused FS out variables as being statically assigned.
I only considered var->assigned for FragColor and FragData, but
ignored when it was false for out vars.  Fixes piglit
write-gl_FragColor-and-not-user-output.frag

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49068
2012-05-04 14:00:32 -07:00
Eric Anholt fcd57280ae i965: Add a comment about the state flag for sRGBEnabled.
I thought this might be _NEW_COLOR, but it isn't.
2012-05-04 14:00:32 -07:00
Eric Anholt b7406404ab intel: Return success when asked to allocate a 0-width/height renderbuffer.
It seems silly that GL lets you allocate these given that they're
framebuffer attachment incomplete, but the webgl conformance tests
actually go looking to see if the getters on 0-width/height
depth/stencil renderbuffers return good values.  By failing out here,
they all got smashed to 0, which turned out to be correct for all the
getters they tested except for GL_RENDERBUFFER_INTERNAL_FORMAT.  Now,
by succeeding but not making a miptree, that one also returns the
expected value.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-05-04 14:00:32 -07:00
Eric Anholt 6508b0b9b0 glsl: Always copy the index when cloning a variable.
The index is also used for GL_ARB_blend_func_extended.  Cloning in
i965 was dropping a non-ARB_explicit_attrib_location index.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2012-05-04 14:00:32 -07:00
Eric Anholt b7932e183c i965: Add support for GL_ARB_draw_buffers_blend.
Tested with piglit fbo-draw-buffers-blend and intel oglconform.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-05-04 14:00:32 -07:00
Christoph Bumiller 9ef549d7cd nv50: fix typo causing NULL-deref in nv50_resource_resolve
Introduced in b328949a37.
2012-05-04 18:00:46 +02:00
Christoph Bumiller dffc2fb4e6 nv50/ir: move expansion of IMUL to later stage and handle memory operands 2012-05-04 18:00:40 +02:00
Christoph Bumiller 02fac29305 nv50: implement stream output 2012-05-04 18:00:07 +02:00
Christoph Bumiller 8a44ecdae8 nv50: enable array textures 2012-05-04 18:00:03 +02:00
Brian Paul c66dc0ea8e svga: specify 4-byte aligned vertex elements
We haven't found a case where this is needed, but it would be prudent
for some hosts, per Jose.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-05-04 08:12:53 -06:00
Brian Paul e039fd079b gallivm: fix comment typo 2012-05-04 08:07:58 -06:00
Brian Paul a0c380a744 docs: another viewperf bug 2012-05-04 08:07:58 -06:00
Brian Paul a36581ccc0 mesa: do more teximage error checking for generic compressed formats
When glTexImage or glCopyTexImage is called with internalFormat being a
generic compressed format (like GL_COMPRESSED_RGB) we need to do the same
error checks as for specific compressed formats.  In particular, check if
the texture target is compatible with the format.  None of the texture
compression formats we support so far work with GL_TEXTURE_1D, for example.

See also https://bugs.freedesktop.org/show_bug.cgi?id=49124

NOTE: This is a candidate for the 8.0 branch.
2012-05-04 08:07:58 -06:00
Vinson Lee 5cc4b4aaf4 scons: Do not build EGL on Solaris.
The current EGL headers do not support Solaris.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-05-03 22:58:35 -07:00
Jeremy Huddleston 51691f0767 darwin: Use ASL for logging
Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
2012-05-03 10:58:34 -07:00
Jeremy Huddleston cf5db0a418 darwin: Make reported errors more user-friendly
Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
2012-05-03 10:58:33 -07:00
Jeremy Huddleston 244dc05214 darwin: Fix an error message
Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
2012-05-03 10:58:33 -07:00
Robert Hooker c384c5d4d7 egl_dri2: Fix out of tree builds with the wayland backend enabled
Otherwise it fails like so:

  CC     egl_dri2.lo
In file included from egl_dri2.h:40:0,
                 from egl_dri2.c:42:
../../../../../../src/egl/wayland/wayland-drm/wayland-drm.h:8:41:
fatal error: wayland-drm-server-protocol.h: No such file or directory
compilation terminated.
2012-05-03 11:45:59 -04:00
Kristian Høgsberg 4fddb2ba21 gbm: Add gbm_bo_write entry point
This new gbm entry point allows writing data into a gbm bo.  The bo has
to be created with the GBM_BO_USE_WRITE flag, and it's only required to
work for GBM_BO_USE_CURSOR_64X64 bos.

The gbm API is designed to be the glue layer between EGL and KMS, but there
was never a mechanism initialize a buffer suitable for use with KMS
hw cursors.  The hw cursor bo is typically not compatible with anything EGL
can render to, and thus there's no way to get data into such a bo.

gbm_bo_write() fills that gap while staying out of the efficient
cpu->gpu pixel transfer business.

Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
2012-05-03 10:57:32 -04:00