KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

radeon/llvm: add support for v4i32 

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
This commit is contained in:
Vadim Girlin 2012-05-07 20:24:13 +04:00
parent 06db74a753
commit 757f471ba9
4 changed files with 20 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp
View File

@ -27,7 +27,7 @@ namespace {
private:
static char ID;
TargetMachine &TM;
void lowerVCREATE_v4f32(MachineInstr &MI, MachineBasicBlock::iterator I,
void lowerVCREATE_v4(MachineInstr &MI, MachineBasicBlock::iterator I,
MachineBasicBlock &MBB, MachineFunction &MF);
public:
@ -56,8 +56,9 @@ bool AMDGPULowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
switch (MI.getOpcode()) {
default: continue;
case AMDIL::VCREATE_v4f32: lowerVCREATE_v4f32(MI, I, MBB, MF); break;
case AMDIL::VCREATE_v4f32:
case AMDIL::VCREATE_v4i32:
lowerVCREATE_v4(MI, I, MBB, MF); break;
}
MI.eraseFromParent();
}
@ -65,7 +66,7 @@ bool AMDGPULowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
return false;
}
void AMDGPULowerInstructionsPass::lowerVCREATE_v4f32(MachineInstr &MI,
void AMDGPULowerInstructionsPass::lowerVCREATE_v4(MachineInstr &MI,
MachineBasicBlock::iterator I, MachineBasicBlock &MBB, MachineFunction &MF)
{
MachineRegisterInfo & MRI = MF.getRegInfo();

2
src/gallium/drivers/radeon/R600GenRegisterInfo.pl
View File

@ -81,7 +81,7 @@ def R600_Reg32 : RegisterClass <"AMDIL", [f32, i32], 32, (add
R600_CReg32,
ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF)>;
def R600_Reg128 : RegisterClass<"AMDIL", [v4f32], 128, (add
def R600_Reg128 : RegisterClass<"AMDIL", [v4f32, v4i32], 128, (add
$t128_string)>
{
let SubRegClasses = [(R600_TReg32 sel_x, sel_y, sel_z, sel_w)];

4
src/gallium/drivers/radeon/R600ISelLowering.cpp
View File

@ -25,9 +25,13 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
// setSchedulingPreference(Sched::VLIW);
addRegisterClass(MVT::v4f32, &AMDIL::R600_Reg128RegClass);
addRegisterClass(MVT::f32, &AMDIL::R600_Reg32RegClass);
addRegisterClass(MVT::v4i32, &AMDIL::R600_Reg128RegClass);
addRegisterClass(MVT::i32, &AMDIL::R600_Reg32RegClass);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Legal);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
}
MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(

10
src/gallium/drivers/radeon/R600Instructions.td
View File

@ -938,6 +938,16 @@ def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
include "R600ShaderPatterns.td"