Commit Graph

133048 Commits

Author SHA1 Message Date
Mauro Rossi 6a2ae4e35c android: pan/bi: Generate builder routines
Fixes the following building error:

external/mesa/src/panfrost/bifrost/bifrost_compile.c:38:10: fatal error: 'bi_builder.h' file not found
         ^~~~~~~~~~~~~~
1 error generated.

Fixes: 8ef0d41170 ("pan/bi: Generate builder routines")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8294>
2021-01-04 17:32:31 +00:00
Mauro Rossi 0fb8223f29 android: pan/bi: Generate instruction printer
To avoid building errors in Android

Fixes: 1893a3805e ("pan/bi: Generate instruction printer")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8294>
2021-01-04 17:32:31 +00:00
Samuel Pitoiset 3ae1c6a4fb radv: disable A2 SNORM/SSCALED/SINT for texel buffers & images on all gens
AMDVLK and AMDGPU-PRO also don't support these formats for texel
buffers and images.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3386
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8315>
2021-01-04 17:19:41 +00:00
Rhys Perry b2d000513e aco: fix incorrect address calculation for load_barycentric_at_sample
Fix address calculation for indirect load_barycentric_at_sample on GFX6-8
with a uniform sample index.

A non-zero uniform sample index does not seem to be tested by CTS.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3966
Fixes: 93c8ebfa78 ("aco: Initial commit of independent AMD compiler")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8302>
2021-01-04 16:53:29 +00:00
Alyssa Rosenzweig b32834e5f7 pan/bi: Fix TEXS register counts
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: cffc1d90da ("pan/bi: Add staging register counts to ISA.xml")
Reported-by: Icecream95
Tested-by: macc24
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8310>
2021-01-04 16:41:55 +00:00
Boris Brezillon 20f7a73a2c panfrost: Allow 3D AFBC on Bifrost v7
This feature doesn't seem to work properly on Midgard, and is flagged
as unsupported on Bifrost v6.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 4ffe73547d panfrost: Fix calculation of body/header pointers for 3D AFBC
When using 3D AFBC, all headers are placed at the beginning instead of
being interleaved with each surface body, which forces us to adjust
the calculation in that case.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon a6b269a39d panfrost: Allow AFBC on 2D arrays
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon f901de6b06 panfrost: Fix panfrost_should_linear_convert()
Take 3D/array textures into accound when checking for entire overwrite.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 72444d4d28 panfrost: Initialize AFBC headers to zero
This way we can load uninitialized AFBC surfaces without causing GPU
faults.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 3c92abe359 panfrost: Use panfrost_get_layer_stride() instead of open-coding it
If we don't do that we don't account for CRC buffers.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 8a9b2ef82d panfrost: Enable AFBC support on Bifrost
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 8a677cea0a panfrost: Fix AFBC support on Bifrost
Bifrost and Midgard render target and ZS extension descriptors are a bit
different, adjust the code to take those differences into account.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon dc664d5fb8 panfrost: Use proper format for Z16_UNORM
R16_UNORM isn't compatible with AFBC, we need to use the native Z16
format if we want to allow AFBC on those resources.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon ebeb361350 panfrost: Fix ZS block format v7 definition
This field takes 4 bits, not 2.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 44217be921 panfrost: Adjust the format for AFBC textures on Bifrost v7
On Bifrost v7, AFBC textures can't be used with a non-identity component
order. Let's patch the format so the component order is always RGB[A].
That means we're lying about the internal format, but that shouldn't be
a problem as long as we don't share the resource.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 256d4a3eee panfrost: Pass a pipe-like swizzle to panfrost_new_texture()
And let the function translate it to a mali swizzle. This way we will
be able to adjust the swizzle if needed.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon e91cb99ec6 panfrost: Add R5G6B5_UNORM entries to the format tables
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 5d4a1bc709 panfrost: Adjust surface stride calculation to take AFBC into account
AFBC strides are different from tiled/linear stride and we need to
use the value defined in slice.afbc.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon e8b997e175 panfrost: Add AFBC slice.body_size and slice.{row,surface}_stride fields
Those are needed for render target and texture descriptors and can't be
easily extracted from the other fields present in panfrost_slice

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 7e37a31741 panfrost: Fix AFBC header_size and slice size calculation
3D AFBC textures have their AFBC headers grouped together at the
beginning of the buffer which means the header_size should be multiplied
by the depth. 2D arrays have their AFBC headers placed at the beginning
of each slice, meaning that the slice size should take them into account.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon a9a3b0e21f panfrost: Move AFBC header_size to a sub-struct
So we can add more AFBC related fields under this struct.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 4dd7991422 panfrost: Add a pan_image_layout object
Group the slices, dimension, modifier and array stride in a an object
representing the image layout. This way we shrink the number of
arguments passed to various pan_texture helpers and simplifies some
of the logic along the way.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon e9e823ec83 panfrost: Stop mixing depth and number of samples
Texture depth and MSAA are two different concepts even if they are
exclusive on Mali GPUs (depth field is repurposed for sample index
there). Let's not mix them and adjust the slice_full_size calculation
to take both into account.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 728069485d panfrost: Use PAN_V6_SWIZZLE() in pan_blit.c
Suggested-by: Icecream95
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 25eb7c52dc panfrost: s/panfrost_slice.size0/panfrost_slice.surface_stride/
This field is encoding the stride between two consecutive surface
in a 3D texture. Let's use a name reflecting that.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 284c43ed4b panfrost: Merge panfrost_new_texture() and panfrost_new_texture_bifrost()
There's no reason to keep both now that the internal logic has been
deduplicated.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 1fd3861a71 panfrost: Adjust the compression tag creation for Bifrost
Bifrost has a few more compression flags that are worth specifying.
Extend panfrost_compression_tag() to deal with those too.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon def5fb9f5e panfrost: Define AFBC surface flags
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon ca265b48d9 panfrost: Pass a dev object to panfrost_needs_explicit_stride()
So we can soon use the same path for Bifrost and Midgard.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon ab1dec8dd4 panfrost: Merge emit_texture_payload() and emit_texture_payload_v7()
The only reason we have two different functions to prepare the texture
payload is the different ordering between pre-v7 and v7+ GPUs. Abstract
the surface iteration so we can merge panfrost_emit_texture_payload_v7()
and panfrost_emit_texture_payload().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 062dde4151 panfrost: Pass a device object to panfrost_new_texture()
We will need it to merge some of the Bifrost and Midgard logic.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon 3c5fd5509f panfrost: Group CRC fields in a struct
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Boris Brezillon cbf68b21fb panfrost: Move checksum_bo to panfrost_resource
There's no reason to have the checksum_bo at the slice level since there
can only be one external CRC BO per resource. Move this field to the
panfrost_resource struct.

Suggested-by: Icecream95
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
2021-01-04 17:05:42 +01:00
Mike Blumenkrantz 9ab45f4a63 features: mark off textureGather for zink
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8151>
2021-01-04 15:55:17 +00:00
Mike Blumenkrantz c28ca18991 zink: enable PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8151>
2021-01-04 15:55:17 +00:00
Mike Blumenkrantz 1ebba319cf zink: handle textureGather with Shadow-type samplers
these have to go through OpImageDrefGather without composite construction
on the result

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8151>
2021-01-04 15:55:17 +00:00
Mike Blumenkrantz 03a9a063e5 zink: implement ARB_texture_gather
again pretty straightforward, just hooking up tg4 tex op in ntv

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8151>
2021-01-04 15:55:17 +00:00
Mike Blumenkrantz fd39bf6c06 zink: use Offset param for txf ops
there's an image operand for handling offsets, so we can use this when it
hasn't previously been lowered away

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8151>
2021-01-04 15:55:17 +00:00
Mike Blumenkrantz 6bbd7cc370 zink: run nir_lower_tex for offsets if shaderImageGatherExtended is missing
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8151>
2021-01-04 15:55:17 +00:00
Danylo Piliaiev 81132983cd nir: fix missing nir_lower_pntc_ytransform.c in the makefile
Fixes: 33fd9e5d "nir: account for point-coord origin when lowering it"
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8308>
2021-01-04 15:37:20 +00:00
Mike Blumenkrantz 9c18491e41 zink: handle dynamic sampler array indexing for arb_gpu_shader5
this requires that arrays of samplers be declared as single variables with
a single binding point, which is then propagated through to the descriptor
set updates

constant sampler array indexing is now un-lowered during access so we can
construct an access chain for both constant and dynamic offset paths

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8155>
2021-01-04 15:01:59 +00:00
Mike Blumenkrantz 1a7b7b17ad radv: avoid oob read during clear
when clearing a depth/stencil image the passed colorvalue pointer is
smaller than the VkClearValue struct size

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8288>
2021-01-04 14:11:56 +00:00
Danylo Piliaiev 33fd9e5d8a nir: account for point-coord origin when lowering it
The resulting point-coord origin not only depends on whether
the draw buffer is flipped but also on GL_POINT_SPRITE_COORD_ORIGIN
state. Which makes its transform differ from a transform of wpos.

On freedreno fixes:
 gl-3.2-pointsprite-origin
 gl-3.2-pointsprite-origin -fbo

Fixes: d934d320 "nir: Add flipping of gl_PointCoord.y in nir_lower_wpos_ytransform."
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8200>
2021-01-04 13:41:33 +00:00
Bas Nieuwenhuizen 3898f747ce radv: Use VRAM for the initial gfx cmdbuffer.
Not expect it to make any real difference, but lets be consistent.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7979>
2021-01-04 13:10:16 +00:00
Bas Nieuwenhuizen b7cc5dc853 radv: Put commandbuffers in VRAM if all VRAM is CPU visible.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7979>
2021-01-04 13:10:15 +00:00
Bas Nieuwenhuizen f06e91d85a radv: Use VRAM for upload buffers if entire VRAM is CPU-visible.
Not doing this for APUs because spilling is quite likely, due to
overall VRAM pressure.

Also adding a flag to disable for performance debugging.

Finally adds some memset for places where we depended on the memory
being initialized to zero, which we won't get with VRAM anymore.
(I think these places should stop depending on it since it hides
 issues with executing the cmdbuffer multiple times, but this
  preserves behavior)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7979>
2021-01-04 13:10:15 +00:00
Jesse Natalie 24dcdc3fa9 microsoft/compiler: Fix clang fallthrough warnings
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8248>
2021-01-03 23:07:21 +00:00
Jesse Natalie 72d7e173e3 microsoft/resource_state_manager: Remove unused private variable
Clang detects that this variable is unused. We can re-add it if
we end up needing it but for now let's just remove it.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8248>
2021-01-03 23:07:21 +00:00
Jesse Natalie c11f2f5de8 microsoft/compiler: Fix tautological comparison
Clang detects that a signed character can't be >= 128. Instead,
we should just explicitly check for the 8th bit via bitmask compare.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8248>
2021-01-03 23:07:21 +00:00