Dan Nicholson
817af9bec2
glapi: Use variable for indent and flags
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Put the path to indent and the flags to call it with in configs/default
rather than in the Makefile. This makes it easier to change the values
globally.
2008-02-12 06:43:23 -08:00
Ben Skeggs
532828b1d3
nouveau: ddx versioning changed
2008-02-12 17:28:31 +11:00
Claudio Ciccani
2c9fdaf729
[directfb] Added RGB444 and RGB555.
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Also added color expansion for RGB16, ARGB1555 and ARGB4444.
2008-02-08 12:36:45 +01:00
Claudio Ciccani
c231f8ff35
[glut-directfb] Fixed displaying of single buffered window.
2008-02-08 12:35:08 +01:00
Claudio Ciccani
5edede94bb
[glut-directfb] When converting microseconds to milliseconds, round to the next integer.
2008-02-08 12:03:53 +01:00
Eric Anholt
70908a793b
[965] Flush icache on new batch, not just new context.
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This is required since our buffer manager may now move our
instruction-containing buffers at any batchbuffer emit.
2008-02-07 13:14:59 -08:00
Andy Skinner
5c0c883104
added -altopts to allow overriding all other opts
2008-02-07 13:21:14 -07:00
Eric Anholt
700a77fb48
[915] Fix COS function using same plan as SIN.
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The previous COS function failed badly outside of [-pi/2, pi/2].
2008-02-06 15:43:05 -08:00
Eric Anholt
2551a5ee80
[915] Use a quartic term to improve the accuracy of SIN results.
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This is described in the link in the comment, and is the same technique that
r300 uses.
2008-02-06 15:40:32 -08:00
Eric Anholt
d98abcbef0
[915] Fix fp SIN function, and use a quadratic approximation instead of Taylor.
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The Taylor series notably fails at producing sin(pi) == 0, which leads to
discontinuity every 2*pi. The quadratic gets us sin(pi) == 0 behavior, at the
expense of going from 2.4% THD with working Taylor series to 3.8% THD (easily
seen on comparative graphs of the two). However, our previous implementation
was producing sin(pi) < -1 and worse, so any reasonable approximation is an
improvement. This also fixes the repeating behavior, where the previous
implementation would repeat sin(x) for x>pi as sin(x % pi) and the opposite
for x < -pi.
2008-02-06 15:26:00 -08:00
Eric Anholt
c0e026c809
[965] Bug 14314: assertion failure with with !AIGLX and depth=24 visual.
2008-02-05 11:01:14 -08:00
Eric Anholt
d14d36f9cc
[965] Fix TTM relocation caching overzealousness.
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The failure mode that was a available was:
reloc 1 -> target_buf
exec: PRESUMED_OFFSET wrong, buffer migrates, r1 entry updated.
reloc 2 -> target_buf
exec: suppose buffer migrates again. PRESUMED_OFFSET wrong. r2 entry updated.
reloc 1 -> target_buf
exec: suppose buffer doesn't migrate. PRESUMED_OFFSET right. no relocations
performed. r1 has stale pointer at original location.
Failures were reported with OGLconform's VBO test and SPECviewperf90, though
I haven't confirmed that this fixes it.
2008-02-05 11:01:14 -08:00
Xiang, Haihao
89faa648a5
i965: adjust the byte order of clear color. fix #14165
2008-02-05 15:17:58 +08:00
Eric Anholt
fd776e10b3
Replace usage of DRM_BO_FLAG_MEM_TT in intel_regions.c with local/cached.
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In addition to potentially binding when it was about to be mapped anyway,
failure to use CACHED_MAPPED means eating a full wbinvd on validate. Thanks to
airlied for catching this.
2008-02-04 18:24:16 -08:00
Eric Anholt
745df749cc
Include glext.h in the cva test so that it actually uses CVAs.
2008-02-04 18:24:16 -08:00
Eric Anholt
5857e988be
Allow first != 0 in mesa CVA handling, and add more error checking.
2008-02-04 18:24:16 -08:00
Eric Anholt
2abcc512a3
[965] Convert brw_draw_upload to managing dri_bos, not gl_buffer_objects.
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This helps us avoid a bunch of mess with gl_client_arrays that we filled
with unused data and confused readers.
2008-02-04 18:24:16 -08:00
Eric Anholt
0907c639c8
[965] Remove dead structure in brw_draw_upload.c.
2008-02-04 18:24:16 -08:00
Eric Anholt
7b8892f504
[965] Move temporary vbo array storage into the function using it.
2008-02-04 18:24:16 -08:00
Eric Anholt
c86ec87830
[965] Remove dead brw_vertex_element members.
2008-02-04 18:24:16 -08:00
Eric Anholt
4e13067d0f
[965] Add a wrapper around interleaved copy_array_to_vbo_array for profiling.
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If compiled with optimization, it shouldn't appear at all, and helps me for
now.
2008-02-04 18:24:16 -08:00
Eric Anholt
df44fefced
[965] Avoid overloaded use of the term 'input' for clarity.
2008-02-04 18:24:16 -08:00
Eric Anholt
931685e243
[965] Replace VEP/VBP state structures with inline batch emits.
2008-02-04 18:24:15 -08:00
Dave Airlie
4dfcb09960
r300: fix isosurf on rs690
2008-02-04 21:59:26 +11:00
Xiang, Haihao
e36857d841
i965: fix potential NULL pointer dereference. The third region
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isn't created at all for 965
2008-02-03 20:36:17 +08:00
Eric Anholt
30c9d96ebf
[965] Fix indentation.
2008-02-01 16:05:10 -08:00
Eric Anholt
f85d34e425
Revert "intel: don't apply the relocation optimization if a target"
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This reverts commit e2cb905bc6
.
It was a reversion of an optimization hidden as otherwise.
pre_target_buf_handle was always NULL, so the optimization was never enabled,
rather than fixing the important optimization (resulting in 25-50% performance
loss).
2008-02-01 16:02:37 -08:00
Eric Anholt
7eca6be25f
[965] Replace XXX comment about constant swizzle with an assert.
2008-02-01 16:02:37 -08:00
Eric Anholt
61760105df
[965] Fix some indentation in brw_vs_tnl.c.
2008-02-01 16:02:36 -08:00
Xiang, Haihao
ca8d91610f
mesa: re-define NEED_SECONDARY_COLOR. fix #14310 .
2008-02-02 00:56:51 +08:00
Zou Nan hai
746db75cfb
[intel] fix for previous fix
2008-02-01 20:28:26 +08:00
Zou Nan hai
a9a483b43e
[intel] use _mesa_copy_rect for upload compressed texture,
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this fix bad texture issue in some games(UT and quake).
2008-02-01 17:36:56 +08:00
Xiang, Haihao
71f53a22d0
i965: Don't emit state if fall back to software rendering. fix #14116
2008-02-01 16:48:16 +08:00
Zou Nan hai
3158e981f5
[i965] renable regative rhw test
2008-01-31 18:22:19 +08:00
Xiang, Haihao
e2cb905bc6
intel: don't apply the relocation optimization if a target
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buffer is used for a relocatee in the former relocation process
then another target buffer is used for this relocatee at the same
offset in the current relocation process.
2008-01-31 17:29:52 +08:00
Roland Scheidegger
01f59153b5
regenerate glsl library functions
2008-01-31 01:43:13 +01:00
Roland Scheidegger
4cc0663564
fix w component of glsl vec4 asin
2008-01-31 01:43:13 +01:00
Brian
2f7c804952
check if fb->Delete is null (bugs 13507,14293)
2008-01-30 08:12:42 -07:00
Alex Deucher
80efe27560
Add new RV380 pci id
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bug 14289
2008-01-29 10:14:04 -05:00
Xiang, Haihao
8e444fb9e2
i965: new integrated graphics chipset support
2008-01-29 11:13:53 +08:00
Brian
f09b2382e9
push out far clip plane to 200
2008-01-28 12:41:47 -07:00
Brian
e7007c6fb0
Added d/D keys to change viewing distance, 'a' to toggle animation
2008-01-28 12:36:01 -07:00
Dave Airlie
3bfef64800
r300: add initial rs690 support to Mesa
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The rs690 has an rs4xx style vertex-shader less 3D engine. It uses the new
r500 output engine though. It also needs a new drm with rs690 support,
which is just getting cleaned up.
2008-01-27 12:16:06 +10:00
Xiang, Haihao
da60fd1291
i965: valid message length includes message header.
2008-01-25 16:52:08 +08:00
Xiang, Haihao
fc81f42817
i965: re-define the type of reg.loopcount.
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avoid some issues such that 1 + (-2) gets a big
positive value.
2008-01-25 16:38:38 +08:00
Eric Anholt
f0310f7636
Bufmgr cleanup from intel-batchbuffer branch of 2d driver.
2008-01-24 13:00:13 -08:00
Eric Anholt
5f0d76204d
Clean up comments/dead code from relocation buffer change.
2008-01-24 12:29:04 -08:00
Eric Anholt
8931585d2c
Merge commit 'airlied/i915-ttm-cfu'
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This requires current DRM which changes the relocation buffer from being a
buffer object to plain malloced memory.
2008-01-24 12:28:42 -08:00
Brian
b87c1ab2c0
Bring in previous 7.0.1/2 release notes, added Cell driver page.
2008-01-24 09:15:31 -07:00
Dave Airlie
a018abd446
i915: move to using copy from user for relocations
2008-01-24 14:38:50 +10:00