Commit Graph

150783 Commits

Author SHA1 Message Date
Lionel Landwerlin 214092da87 anv: fix fast clear type value with external images
Disable fast clear if not supported by the external modifier.

v2: Set fast_clear value to NONE in case of import/export from/to external

v3: Move logic next to existing acquire/release checks (Nanley)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6056
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15096>
2022-03-01 17:37:13 +00:00
Oleksandr Gabrylchuk 02fab4cf9e venus: Implement guest vram blob type.
Add support of GUEST_VRAM type of blob. These are dedicated heap memory
allocations required for vk support on hypervisors that don't support
runtime injections of host memory into guest physical address space.

The flow of usage:
1) Host VM reserves dedicated heap memory
2) Device get info about memory reservations and report it to guest
using mmio registers
3) Guest virtio-gpu driver on starts checks mmio registers for
physical address and length of reserved region. Then it reserves it
in guest.
4) On each call of vkAllocateMemory() guest driver gets chunk of
required memory and send it to host using sg list. It uses one sg
entry for 1 blob call. Heap is managed on guest using drm memory
manager (drm_mm).

Signed-off-by: Oleksandr.Gabrylchuk <Oleksandr.Gabrylchuk@opensynergy.com>
Signed-off-by: Andrii Pauk <Andrii.Pauk@opensynergy.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14536>
2022-03-01 17:25:56 +00:00
Marek Olšák fd3451babd amd: update addrlib
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
2022-03-01 17:03:00 +00:00
Marek Olšák f8cf5ea982 amd: add support for gfx1036 and gfx1037 chips
Both are identified as GFX1036 for simplicity.

Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
2022-03-01 17:03:00 +00:00
Marek Olšák 48046d5bd8 ac: set correct cache size per TCC for Yellow Carp
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
2022-03-01 17:03:00 +00:00
Samuel Pitoiset 4380916b76 radv: disable DCC for Fable Anniversary, Dragons Dogma, GTA IV and more
Also Starcraft 2 and The Force Unleashed II.

These games are known to be affected by the feedback loop issue. We will
fix this properly soon but as a hotfix disabling DCC should be enough.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4424
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15203>
2022-03-01 16:33:18 +00:00
Vadym Shovkoplias dc921f7377 iris: Do not apply SCANOUT allocation flags for SHARED-only requests
It provides similar solution as in [1].

This was workaround for the users of gbm_bo_create_with_modifiers(),
which were unable to specify the buffer usage (GPU / GPU+DISPLAY).

But after the commit [2] this become possible. And forcing usage to
GBM_BO_USE_SCANOUT migrated directly into gbm_bo_create_with_modifiers
[3], allowing us to remove such workarounds from the drivers.

[1]: ef3b31c9 ("v3d: Don't force SCANOUT for PIPE_BIND_SHARED requests")
[2]: 268e12c6 ("gbm: add gbm_{bo,surface}_create_with_modifiers2")
[3]: ad50b47a ("gbm: assume USE_SCANOUT in create_with_modifiers")

Suggested-by: Roman Stratiienko <roman.o.stratiienko@globallogic.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5642
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14264>
2022-03-01 16:04:44 +00:00
Timur Kristóf 93087f71e6 ac/nir: Extract final mesh shader output counts to a separate function.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
2022-03-01 15:37:12 +00:00
Timur Kristóf 11957d3863 aco: Remove superfluous code for mesh shader workgroup ID.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
2022-03-01 15:37:12 +00:00
Timur Kristóf 2d5aae032b ac/nir: Properly invalidate mesh shader metadata.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
2022-03-01 15:37:12 +00:00
Timur Kristóf 3a3bd9cff1 ac/nir: Fix workgroup ID in mesh shader waves other than the first.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
2022-03-01 15:37:12 +00:00
Timur Kristóf 57775dd76a ac/nir: Store mesh shader API and HW workgroup size in lowering state.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
2022-03-01 15:37:12 +00:00
Timur Kristóf d0f45c7c49 ac/nir: Reuse existing nir_builder for emit_ms_finale.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
2022-03-01 15:37:12 +00:00
Timur Kristóf 74f1e7965e ac/nir: Use vertex count minus 1 to determine max index in mesh shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
2022-03-01 15:37:12 +00:00
Charlie Turner 16b417b8d6 ci, valve: Add the dEQP runners for Valve CI
v2.

  - Build the runner image as part of the CI for the boot2container
  project, rather than as a manually step using the build instructions
  in valve-trigger.dockerfile.

  - Depend on a non-default kernel build hosted in the valve-infra
  package repository. This does reduce the current caching feature of
  local artifacts, but makes it easier to chop and change kernels on a
  per-project or even per-test basis.

v3.

  - Depend on a kernel built and stored in the valve-infra generic
  package repo.

  - Build the runner container using ci-templates as part of the CI in
  valve-infra.

  - Now that the runner container is built in the valve-infra CI, I
  dropped the source import of client.py and message.py. They are
  built in the runner container.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
2022-03-01 13:04:14 +00:00
Charlie Turner f0aee991bf amd, ci: Categorize the sections of the CI file.
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
2022-03-01 13:04:14 +00:00
Charlie Turner 58186df32c amd, ci: Drop log level in SPIRV -> NIR code generator.
See 786fa3435c for the rationale of this variable, but the point is to
avoid many error reports for conformance conformance issues within the
VK-CTS shaders.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
2022-03-01 13:04:14 +00:00
Charlie Turner cc327a0fe4 amd, ci: Remove unused runners.
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
2022-03-01 13:04:14 +00:00
Charlie Turner befe3a9e48 ci, valve: Add support scripts for the Valve bare-metal farm.
- Add the scripts to the prepared Mesa artifacts for use in later
runner stages.

- Add a template generator (generate_b2c.py) which reads and
validates (very lightly for now) the Gitlab job environment and then
spits out a YAML file describing the necessary test workload to be
sent to a Valve CI gateway.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
2022-03-01 13:04:14 +00:00
Samuel Pitoiset 1e010348ee radv: remove color exports in presence of holes
If there is holes, eg. if only MRT0 and MRT2 are exported, we have to
set MRT1 to SPI_SHADER_32_R to avoid a GPU hang but the export can
still be removed from the fragment shader.

fossils-db (Sienna Cichlid):
Totals from 565 (0.42% of 134913) affected shaders:
VGPRs: 13328 -> 11456 (-14.05%)
CodeSize: 613232 -> 548224 (-10.60%); split: -11.13%, +0.53%
LDS: 284672 -> 296960 (+4.32%)
MaxWaves: 17624 -> 17684 (+0.34%)
Instrs: 113056 -> 100445 (-11.15%); split: -11.68%, +0.53%
Latency: 684327 -> 639348 (-6.57%); split: -7.17%, +0.60%
InvThroughput: 122877 -> 104382 (-15.05%); split: -15.18%, +0.13%
VClause: 2601 -> 2323 (-10.69%); split: -10.77%, +0.08%
SClause: 5629 -> 5443 (-3.30%); split: -3.91%, +0.60%
Copies: 9393 -> 8720 (-7.16%); split: -8.22%, +1.05%
PreSGPRs: 14623 -> 13666 (-6.54%); split: -6.76%, +0.22%
PreVGPRs: 9847 -> 8503 (-13.65%)

fossils-db (Polaris10):
Totals from 565 (0.42% of 135960) affected shaders:
SGPRs: 28064 -> 27104 (-3.42%)
VGPRs: 12516 -> 10544 (-15.76%); split: -15.79%, +0.03%
CodeSize: 516920 -> 456536 (-11.68%); split: -11.68%, +0.00%
MaxWaves: 4369 -> 4418 (+1.12%)
Instrs: 97771 -> 85903 (-12.14%); split: -12.14%, +0.00%
Latency: 767482 -> 708545 (-7.68%); split: -7.97%, +0.29%
InvThroughput: 280017 -> 235744 (-15.81%)
VClause: 2270 -> 2090 (-7.93%); split: -8.50%, +0.57%
SClause: 5185 -> 5012 (-3.34%); split: -3.86%, +0.52%
Copies: 8328 -> 7555 (-9.28%); split: -9.35%, +0.07%
Branches: 1143 -> 1113 (-2.62%)
PreSGPRs: 13816 -> 12725 (-7.90%); split: -7.92%, +0.02%
PreVGPRs: 9707 -> 8270 (-14.80%)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15108>
2022-03-01 12:28:47 +01:00
Rhys Perry f800af2231 ac/nir: remove TCS nir_var_shader_out memory barrier
nir_var_shader_out writes are only used for later TES invocations, so I
don't think there's any need for the TCS workgroup to wait for them.

fossil-db (Sienna Cichlid):
Totals from 1691 (1.04% of 162293) affected shaders:
Instrs: 710699 -> 709008 (-0.24%)
CodeSize: 3830168 -> 3823404 (-0.18%)
Latency: 3396997 -> 3007934 (-11.45%)
InvThroughput: 1212094 -> 1082823 (-10.67%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15195>
2022-03-01 11:02:43 +00:00
Caio Oliveira 7460199a2f intel/compiler: Lower Task/Mesh I/O before SIMD specific lowering
These are the same for all variants, so just lower it before cloning
the nir_shader for each of them.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15019>
2022-03-01 07:35:13 +00:00
Danylo Piliaiev 549e861dc1 turnip: Implement VK_EXT_physical_device_drm
Copied from ANV and V3DV.

v1. Fix a build error for clang "unannotated fall-through between switch labels"
( Hyunjun Ko <zzoon.ko@igalia.com> )

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6011

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14971>
2022-03-01 07:10:40 +00:00
Pierre-Eric Pelloux-Prayer bb6ba8f21f radeonsi/drirc: use force_gl_vendor for Maya
Otherwise OpenCL initialization fails with "unknown vendor id 0".

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15151>
2022-03-01 07:43:26 +01:00
Ilia Mirkin d3196bac51 nouveau: add dEQP/GLCTS run failure info for GF108/GT215
I happened to have these plugged in. Ran them against mesa 21.3 and
recent VK-GL-CTS tree (shortly after vulkan-cts-1.2.8).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14797>
2022-02-28 22:36:31 -05:00
Nanley Chery dc05615ec1 Revert "anv: Require the local heap for CCS on XeHP"
This reverts commit 382f6ccda8.

The spec requires that all color images created with the same tiling
(and a few other properties) support the same memoryTypeBits. So this
wasn't a valid change. It also wasn't necessary - we already have a
mechanism in anv_BindImageMemory2 for disabling compression if the BO
doesn't support it.

With this, XeHP passes the tests in
dEQP-VK.memory.requirements.*tiling_optimal

Fixes: 382f6ccd ("anv: Require the local heap for CCS on XeHP")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>
2022-03-01 00:02:51 +00:00
Nanley Chery 203c8be09f anv: Add a perf warning in anv_BindImageMemory2
It reports: "BO lacks implicit CCS. Disabling the CCS aux usage."

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>
2022-03-01 00:02:51 +00:00
Nanley Chery 74e446b45b anv: Fall back to HiZ when disabling CCS on HiZ+CCS
When an image configured for HIZ_CCS/HIZ_CCS_WT is bound to a BO lacking
implicit CCS, we disable any compression it may have had. Such images
are still compatible with ISL_AUX_USAGE_HIZ however. Fall back to that
aux usage to retain the performance benefit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>
2022-03-01 00:02:51 +00:00
Nanley Chery ffbde42b93 anv: Don't disable HiZ/MCS in anv_BindImageMemory2
When an image is bound to a BO lacking implicit CCS, we disable any
compression it may have had. This is unnecessary in the cases where the
compression type doesn't depend on the BO having implicit CCS support.
Avoid this disabling for ISL_AUX_USAGE_MCS and ISL_AUX_USAGE_HIZ.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>
2022-03-01 00:02:51 +00:00
Connor Abbott ed9a0d48a9 ir3: Use isam for bindless images
In the bindless case, we don't have to keep any shadow descriptors and
can just reuse the IBO descriptor as a texture descriptor. Now that
we're emitting the swizzle we can just flip this on.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
2022-02-28 23:33:22 +00:00
Connor Abbott 06485f7d3d tu: Call nir_opt_access
This adds some small optimizations, and enables lowering to isam in more
cases where the app didn't specify readonly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
2022-02-28 23:33:22 +00:00
Connor Abbott 58d72f45e5 ir3/nir: Fix 1d array readonly images
ncoords includes the array index, and the NIR source has the array index
as its last component, so we have to insert the extra y coordinate in
the middle in this case.

Fixes: 0bb0cac ("freedreno/ir3: handle image buffer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
2022-02-28 23:33:22 +00:00
Connor Abbott 21ac044c3e ir3: Don't always set bindless_tex with readonly images
Fixes: 274f381 ("ir3: Plumb through bindless support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
2022-02-28 23:33:22 +00:00
Connor Abbott bb1e0eba08 freedreno/fdl: Set swizzle on storage descriptor
It appears to be unused by ldib/stib, but it will let us use isam on IBO
descriptors for bindless images.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
2022-02-28 23:33:22 +00:00
Connor Abbott 00be8c4619 freedreno: Replace A6XX_IBO with A6XX_TEX_CONST
Since these were reverse-engineered, it's become clear that IBO
descriptors are just a subset of texture descriptors, and bindless reads
of readonly images actually use isam on the IBO descriptor, further
confirming that the two are always compatible, even if not all of the
texture fields exist for IBOs. It's pointless to have a separate type
for IBOs, and just leads to things getting out-of-sync unnecessarily
which has already happened. Just remove it and use TEX_CONST insted.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
2022-02-28 23:33:22 +00:00
Connor Abbott e1c4c2ac60 ir3: Use CAN_REORDER instead of NON_WRITEABLE
CAN_REORDER takes volatile into account, and is closer to what we
actually require to use texture instructions, which is that we can
arbitrarily reorder loads.

Fixes: aa93896 ("freedreno/ir3: adjust condition for when to use ldib")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
2022-02-28 23:33:22 +00:00
Danylo Piliaiev 95fabff8de turnip: Set drmFormatModifierTilingFeatures
From Vulkan spec for VkDrmFormatModifierProperties2EXT:

 "drmFormatModifierTilingFeatures is a bitmask of VkFormatFeatureFlagBits
  that are supported by any image created with format and drmFormatModifier."

 "The returned drmFormatModifierTilingFeatures must contain at least one bit."

 "Therefore, if the returned drmFormatModifier is DRM_FORMAT_MOD_LINEAR,
  then drmFormatModifierPlaneCount must equal the format planecount, and
  drmFormatModifierTilingFeatures must be identical to the
  VkFormatProperties2::linearTilingFeatures returned in the same pNext chain."

Relevant tests: dEQP-VK.drm_format_modifiers.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15032>
2022-02-28 22:53:40 +00:00
Mike Blumenkrantz 473f488639 zink: add layer asserts for 3d imageview creation
make sure there's no other mishaps here in the future

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>
2022-02-28 17:42:58 +00:00
Mike Blumenkrantz 8e67928862 zink: more accurately clamp 3d fb surfaces to corresponding 2d target
if more than 1 layer is being bound, this is an array, otherwise it's just
regular 2d

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>
2022-02-28 17:42:58 +00:00
Mike Blumenkrantz 59b0105e65 zink: clamp 3d/array shader images to lower dimensionality using layer counts
this creates the view type expected by the shader instead of doing weird stuff
like trying to create a 3D imageview with layers > 1

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>
2022-02-28 17:42:58 +00:00
Mike Blumenkrantz 26d05e5a38 zink: directly create surfaces for shader images
avoid the implicit clamping of fb surfaces in zink_create_surface()
in order to provide more granularity

no functional changes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>
2022-02-28 17:42:58 +00:00
Mike Blumenkrantz 69ec429c00 zink: restrict clear flushing on sampler/image bind to compute binds
this is otherwise going to be handled on the next renderpass start

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>
2022-02-28 17:42:58 +00:00
Mike Blumenkrantz b7b494299d zink: use VK_EXT_depth_clip_control when available
this saves a few ALUs in vertex stages

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15174>
2022-02-28 17:21:29 +00:00
Mike Blumenkrantz 95708c13ee glx/drisw: handle GL_RESET_NOTIFICATION_STRATEGY
fixes (llvmpipe):
KHR-NoContext.gl45.robustness.lose_context_on_reset

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15061>
2022-02-28 16:10:00 +00:00
Mike Blumenkrantz fba13486df zink: update psiz handling to fix xfb output
now when gl_PointSize and gl_PointSizeMESA are both present, the former
will be used for xfb with a new location and the latter will be
exported by the shader

fixes (zink):
GTF-GL46.gtf30.GL3Tests.transform_feedback.transform_feedback_builtins

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15184>
2022-02-28 15:42:20 +00:00
Mike Blumenkrantz b28cff9f4a nir/lower_psiz_mov: stop clobbering existing exports
for this pass to work with xfb, the original value in the shader must be
preserved when xfb is active, and the driver must export only the newly
created output

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15184>
2022-02-28 15:42:19 +00:00
Mike Blumenkrantz 3267417c22 nir/lower_psiz: create the store instruction more accurately
creating this at the start of the shader means it will get optimized out
when the pass is used to overwrite existing psiz values, and creating it
at the end means it will get optimized out in geometry shaders, so instead
just walk the instructions and create another store right after the existing one

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15184>
2022-02-28 15:42:19 +00:00
Jonathan Gray 6250a3bc18 util: use correct type in sysctl argument
Fixes build on OpenBSD/macppc powerpc

error: incompatible pointer types passing 'int *' to parameter of type 'size_t *'
    (aka 'unsigned long *') [-Werror,-Wincompatible-pointer-types]

Fixes: 01bd21eef8 ("gallium: Import Dennis Smit cpu detection code.")
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6511>
2022-02-28 14:28:23 +00:00
Jonathan Gray 0536b69133 util: fix build with clang 10 on mips64
On mips64, the compiler does not allow use of non-zero argument with
__builtin_frame_address(). However, the returned frame address is only
used when PIPE_ARCH_X86 is defined. The compile error can be avoided
by making #ifdef PIPE_ARCH_X86 cover the getting of frame address too.

The argument checking of __builtin_frame_address() has been present
as a debug assert in clang 8. In clang 10, there is a proper runtime
check for the argument. This is why the build has not failed before.

Fixes: dc94a0506f ("gallium: Do not add -Wframe-address option for gcc <= 4.4.")
from Visa Hankala

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6511>
2022-02-28 14:28:23 +00:00
Jonathan Gray f12c107b03 util/u_atomic: fix build on clang archs without 64-bit atomics
Make this build on clang architectures that don't have 64-bit atomic
instructions.  Clang doesn't allow redeclaration (and therefore
redefinition) of the __sync_* builtins.  Use #pragma redefine_extname
to work around that restriction.  Clang also turns __sync_add_and_fetch
into __sync_fetch_and_add (and __sync_sub_and_fetch into
__sync_fetch_and_sub) in certain cases, so provide these functions as
well.

Fixes: a6a38a038b ("util/u_atomic: provide 64bit atomics where they're missing")
patch from Mark Kettenis

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6511>
2022-02-28 14:28:23 +00:00