Commit Graph

144648 Commits

Author SHA1 Message Date
Francisco Jerez cb9f02f863 iris: Add read-write domain for data cache.
This will allow us to remove the history flushes performed for SSBOs
and instead take advantage of the same mechanism used for tracking
other memory accesses.

v2: Use C99 designated initializers (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12691>
2021-09-02 03:14:37 +00:00
Francisco Jerez c677e76483 iris: Insert buffer-local memory barriers for indirect draw parameters.
This adds buffer-local barriers so any required synchronization
commands are emitted before a buffer object is used as source for
indirect draw parameters.  An unconditional PIPE_CONTROL meant to
flush the contents of the draw count buffer can now be removed, since
it's redundant with the more accurate buffer-local barrier introduced
here, which should avoid flushing in cases where the buffer wasn't
written by any incoherent cache since the last flush.

(Rebased by Kenneth Graunke.)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12691>
2021-09-02 03:14:37 +00:00
Francisco Jerez 51f022cc03 iris: Add separate dirty bit for VBO flushes.
Instead of emitting barriers every time IRIS_DIRTY_VERTEX_BUFFERS is
flagged, use a separate dirty bit and optimize out the barriers in
cases where the same buffer object is re-bound as vertex buffer.

Omitting this commit would lead to the following statistically
significant Piglit Draw Overhead regressions:

 36/DrawElements (16 VBO| 8 UBO|  8 Tex) w/ vertex attrib change:      XXX ±7.22% x22 -> XXX±11.09% x21  d=-20.10% ±8.06%  p=0.00%
 98/DrawArrays (16 VBO| 8 UBO|  8 Tex) w/ vertex attrib change:        XXX ±7.27% x22 -> XXX ±7.70% x21  d=-17.76% ±6.83%  p=0.00%
 69/DrawArrays ( 1 VBO| 8 UBO|  8 Tex) w/ vertex attrib change:        XXX ±9.94% x22 -> XXX ±8.72% x21   d=-7.46% ±9.08%  p=1.02%
 53/DrawElements (16 VBO| 8 UBO|  8 Tex) w/ depth enable change:       XXX ±8.34% x22 -> XXX ±6.88% x21   d=-7.30% ±7.45%  p=0.26%
 61/DrawElements (16 VBO| 8 UBO|  8 Tex) w/ cull face enable change:   XXX±10.22% x22 -> XXX ±8.63% x21   d=-6.75% ±9.23%  p=2.11%
 55/DrawElements (16 VBO| 8 UBO|  8 Tex) w/ stencil enable change:     XXX ±9.30% x22 -> XXX ±7.25% x21   d=-6.60% ±8.16%  p=1.14%
 50/DrawElements (16 VBO| 8 UBO|  8 Tex) w/ viewport change:           XXX ±6.48% x22 -> XXX ±5.93% x21   d=-6.58% ±6.04%  p=0.09%
 54/DrawElements (16 VBO| 8 UBO|  8 Tex) w/ depth clamp enable change: XXX ±9.95% x22 -> XXX ±7.95% x21   d=-6.50% ±8.81%  p=2.02%
 35/DrawElements (16 VBO| 8 UBO|  8 Tex) w/ shader program change:     XXX ±7.27% x22 -> XXX ±7.25% x21   d=-5.77% ±7.06%  p=1.06%

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12691>
2021-09-02 03:14:37 +00:00
Francisco Jerez 4cce00350f iris: Insert buffer-local memory barriers for VF reads.
This ensures that any required synchronization (i.e. PIPE_CONTROL)
commands are emitted whenever a vertex or index buffer is used in
cases where it had been previously accessed from an incoherent caching
domain.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12691>
2021-09-02 03:14:37 +00:00
Francisco Jerez 4ab1048cf9 iris: Annotate all BO uses through VF cache domain.
This promotes some of the previously introduced IRIS_DOMAIN_OTHER_READ
annotations used for vertex data to the more specific
IRIS_DOMAIN_VF_READ domain.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12691>
2021-09-02 03:14:37 +00:00
Francisco Jerez ff601897fb iris: Add read-only domain for VF cache.
This will allow us to order writes and reads of vertex and index
buffers by using the same cache tracking infrastructure introduced
previously for render and depth buffers.  The ultimate goal is to
remove the somewhat heavy-handed history flush mechanism currently
used for buffer objects, and use a single cache tracking mechanism
across the whole driver.

v2: Use C99 designated initializers (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12691>
2021-09-02 03:14:37 +00:00
Mike Blumenkrantz c679dbe09c lavapipe: unbreak imageless framebuffer
vk cmd queue doesn't copy pNext pointers

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12688>
2021-09-01 21:40:00 -04:00
Yiwei Zhang 97aa90dec2 venus: workaround a blob_mem mappable size check issue
For blob_mem allocated from virtgpu_virgl backend, the guest mappable
size queried can be smaller than the size returned from image memory
requirement query from the host side. Here we temporarily workaround
until we switch to use cross-domain backend in minigbm.

Cc: 21.2.3 mesa-stable

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12687>
2021-09-01 22:38:48 +00:00
Yiwei Zhang cbdec34db3 venus: renderer to check map size only when mappable
Cc: 21.2.3 mesa-stable

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12687>
2021-09-01 22:38:48 +00:00
Mike Blumenkrantz ae6a5e8f46 docs: update features for lavapipe
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12627>
2021-09-01 22:01:03 +00:00
Mike Blumenkrantz 9be8c48058 lavapipe: support EXT_primitive_topology_list_restart
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12627>
2021-09-01 22:01:03 +00:00
Paulo Zanoni 89a34cb845 iris: switch to explicit busy tracking
We're moving away from relying on the Kernel's implicit busy tracking
into our own tracking, except for shared buffers.

Not only this shouldn't hurt now (it doesn't, according to my
measurements), when we switch to vm_bind we will be able to cut some
significant overhead by simply omitting all the async buffers from the
execbuf ioctl.

v2:
- Change iris_bo_busy() to bool (Ken).
- Fix coding style issues (Ken).
- Rebase on not having the refcount _inc and _dec helpers anymore
  (Ken).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4748
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12363>
2021-09-01 21:48:13 +00:00
Paulo Zanoni d1c27d214b iris: give each screen of a bufmgr a unique ID
We want to implement explicit BO dependency tracking and for that
we'll use arrays of dependencies (syncobjs) indexed by screen->id.
This is way more efficient than storing and checking screen pointers
everywhere.

v2: Properly use atomic operations in a non-racy way (Alyssa, Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12363>
2021-09-01 21:48:13 +00:00
Paulo Zanoni b2c811ccdc iris: syncobjs are now owned by bufmgr instead of screen
The next patches will justify the new ownership. We want the BOs to
have references on the batches' syncobjs so we can implement implicit
tracking. In other words: BOs will be able to wait on syncobjs owned
by different screens. Since our syncobjs are actually just a Kernel
handle with a refcount, they can be used globally and it makes more
sense to map them to the bufmgr, just like the BOs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12363>
2021-09-01 21:48:13 +00:00
Samuel Pitoiset 971a373caf radv: use radeon_set_sh_reg_seq() more for initial gfx/compute state
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12671>
2021-09-01 20:46:29 +00:00
Chia-I Wu bd04ff972e venus: initialize physical devices once
Avoid re-enumeration when there is no device or no supported device.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12653>
2021-09-01 20:27:50 +00:00
Chia-I Wu 7dfac808b0 venus: no supported device is not an error
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12653>
2021-09-01 20:27:50 +00:00
Chia-I Wu fc74233363 venus: group physical device fields with a struct
This makes it clear what the mutex protects.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12653>
2021-09-01 20:27:50 +00:00
Mike Blumenkrantz 7aef59ccd2 radv: add some asserts for descriptor updating
let's avoid any further issues with descriptor sizing

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12620>
2021-09-01 20:08:24 +00:00
Tomeu Vizoso ec44c48945 vulkan: Remove dependency on Python 3.9+
Closes #5311.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Fixes: 997a6ca226 ("vulkan: Generate entrypoints that enqueue commands")
Fixes: a7b0946ef0 ("vulkan: Generate code to place commands in a queue")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12672>
2021-09-01 19:46:14 +00:00
Connor Abbott 1963a61faa freedreno/computerator: Add support for pvtmem
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11876>
2021-09-01 19:26:41 +00:00
Emma Anholt b16587c14c ci/freedreno: Add a bunch of recent a530 and a630 flakes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12683>
2021-09-01 19:05:53 +00:00
Emma Anholt 41c5dd972e ci/freedreno: Annotate a bunch of piglit fails/crashes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12683>
2021-09-01 19:05:53 +00:00
Mike Blumenkrantz 34f0aef19b radv: just use UINT64_MAX when getting absolute timeout for that value
this would otherwise result in (UINT64_MAX - gettime()), which can effectively
be rounded to UINT64_MAX without a noticeable change

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12680>
2021-09-01 17:47:33 +00:00
Mike Blumenkrantz 45f35900c3 mesa/st: create new surfaces before destroying old ones when updating attachments
try to avoid patterns that would destroy surfaces for drivers that cache them for
deduplication purposes

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12651>
2021-09-01 15:43:48 +00:00
Adrian Bunk 7155676618 util/format: NEON is not available with the soft-float ABI
Fixes: 80923e8d58 ("util/format: Add some NEON intrinsics-based u_format_unpack.")
Reviewed-by: Emma Anholt <emma@anholt.net>
Tested-by: Ross Burton <ross.burton@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12569>
2021-09-01 15:18:02 +00:00
Timur Kristóf fe6e4484ab ac/nir/nggc: Move gs_alloc_req up in NGG culling shaders.
This is the first part of a refactor to make vertex compaction optional.
Additionally, it may yield a very small benefit to allocate the PC
space sligtly sooner.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 58239 (45.27% of 128647) affected shaders:
CodeSize: 160502348 -> 160502340 (-0.00%)
Instrs: 30722664 -> 30722662 (-0.00%)
Latency: 137627419 -> 137782218 (+0.11%); split: -0.00%, +0.11%
InvThroughput: 21698587 -> 21699068 (+0.00%); split: -0.00%, +0.00%
Copies: 3288263 -> 3288261 (-0.00%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12246>
2021-09-01 14:45:14 +00:00
Timur Kristóf f4a65e5628 ac/nir/nggc: Only repack arguments that are needed.
Don't repack everything, only what is actually used.
The goal of this commit is primarily to remove unnecessary
LDS stores and loads. In addition to that, it also gets rid of
a few VALU instructions and reduces VGPR use.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 6951 (5.40% of 128647) affected shaders:
VGPRs: 206056 -> 205360 (-0.34%); split: -0.79%, +0.45%
CodeSize: 12344568 -> 12269312 (-0.61%); split: -0.62%, +0.01%
MaxWaves: 211206 -> 212196 (+0.47%)
Instrs: 2319459 -> 2308483 (-0.47%); split: -0.50%, +0.03%
Latency: 7220829 -> 7164721 (-0.78%); split: -1.21%, +0.43%
InvThroughput: 1051450 -> 1049191 (-0.21%); split: -0.36%, +0.15%
VClause: 25794 -> 25445 (-1.35%); split: -1.97%, +0.61%
SClause: 39192 -> 39277 (+0.22%); split: -0.21%, +0.43%
Copies: 315756 -> 313404 (-0.74%); split: -1.17%, +0.42%
Branches: 127878 -> 127879 (+0.00%); split: -0.00%, +0.00%
PreVGPRs: 168029 -> 160162 (-4.68%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12246>
2021-09-01 14:45:14 +00:00
Timur Kristóf 02bba6aab5 ac/nir/nggc: Don't stop applying reusable variables at prim export.
This was a mistake that prevented reusing variables in shaders
with late primitive export.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 6547 (5.09% of 128647) affected shaders:
VGPRs: 323368 -> 323824 (+0.14%); split: -0.03%, +0.18%
SpillSGPRs: 45 -> 4865 (+10711.11%)
CodeSize: 34208732 -> 33855952 (-1.03%); split: -1.21%, +0.18%
MaxWaves: 142538 -> 142456 (-0.06%); split: +0.04%, -0.09%
Instrs: 6654252 -> 6606432 (-0.72%); split: -0.89%, +0.17%
Latency: 30527770 -> 30452769 (-0.25%); split: -0.42%, +0.18%
InvThroughput: 5604540 -> 5609450 (+0.09%); split: -0.04%, +0.13%
VClause: 121531 -> 120448 (-0.89%); split: -1.17%, +0.27%
SClause: 195388 -> 177902 (-8.95%); split: -9.14%, +0.19%
Copies: 617949 -> 636397 (+2.99%); split: -0.44%, +3.42%
Branches: 228184 -> 228281 (+0.04%); split: -0.09%, +0.13%
PreSGPRs: 271395 -> 343555 (+26.59%); split: -0.01%, +26.60%
PreVGPRs: 277650 -> 277710 (+0.02%); split: -0.01%, +0.03%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12246>
2021-09-01 14:45:14 +00:00
Timur Kristóf 59de9620b4 ac/nir/ngg: Delete unused struct.
This was left there by accident after a rebase mistake.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12246>
2021-09-01 14:45:14 +00:00
Tomeu Vizoso 25720f84df lavapipe: Use c_msvc_compat_args
So local builds fail before the Windows build finds out.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12662>
2021-09-01 16:00:01 +02:00
Danylo Piliaiev 6373dd814a ir3/a6xx,freedreno: account for resinfo return size dependency on IBO_0_FMT
On a6xx resinfo returns size in bytes divided by IBO_0_FMT format size
(not just size in dwords), we have to shift it back to NIR meaning which
is size in bytes.

Make freedreno use 16b buffers when they are supported in order to be
able to depend on hardware capabilities when lowering ssbo size.

Fixes: ce1a381e57 "turnip: enable VK_KHR_16bit_storage on A650"

Fixes cts tests:
    dEQP-VK.ssbo.unsized_array_length.float_offset_explicit_size
    dEQP-VK.ssbo.unsized_array_length.float_no_offset_whole_size
    dEQP-VK.compute.basic.write_multiple_unsized_arr_single_invocation
and many more

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12485>
2021-09-01 16:09:20 +03:00
Mykhailo Skorokhodov e8cbfa95a3 iris: Fix compute shader leak
Variant after creation with the function iris_create_shader_variant
requires to be added to variants. Otherwise there is a memory
leak after execution.

Fixes: 2024d470483("iris: Add the variant to the list as early as possible")
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12645>
2021-09-01 10:02:38 +00:00
Timur Kristóf 9d20cf2732 aco: Fix invalid usage of std::fill with std::array.
In this case std::array doesn't behave like a regular array, therefore
it is NOT okay to index it outside the array, even though std::fill
needs us to do so.

Change the syntax to do the same thing slightly differently,
and add an assertion to make sure the registers are always within
the array's bounds.

Closes: #5289
Fixes: 0e4747d3fb
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12664>
2021-09-01 09:33:28 +00:00
Vinson Lee 498d93f3dd glx: Fix unused-variable warning with macOS build.
../src/glx/tests/indirect_api.cpp:52:20: warning: unused variable 'nil' [-Wunused-variable]
static const void *nil = 0;
                   ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12607>
2021-09-01 09:03:53 +00:00
Timur Kristóf 33630090a2 nir: Add comment to explain the sad_u8x4 opcode.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12649>
2021-09-01 08:42:03 +00:00
Connor Abbott 77a852c1ba lima/gpir: Rewrite register allocation for value registers
The usual linear-scan register allocation algorithm can't handle
preallocated registers, since we might be forced to choose a color for
a non-preallocated variable that overlaps with a pre-allocated variable.
But in such cases we can simply split the live range of the offending
variable when we reach the beginning of the pre-allocated variable's
live range. This is still optimal in the sense that it always finds a
coloring whenever one is possible, but we may not insert the smallest
possible number of moves. However, since it's actually the scheduler
which splits live ranges afterwards, we can simply fold in the move
while keeping its fake dependencies, and then everything still works! In
other words, inserting a live range split for a value register during
register allocation is pretty much free.

This means that we can split register allocation in two. First globally
allocate the cross-block registers accessed through load_reg and
store_reg instructions, which is still done via graph coloring, and then
run a linear scan algorithm over each block, treating the load_reg and
store_reg nodes as referring to pre-allocated registers. This makes the
existing RA more complicated, but it has two benefits: first, using
round-robin with the linear scan allocator results in much fewer fake
dependencies, resulting in around 15 less instructions in the glmark2
jellyfish shader and fixing a regression in instruction count since
branching support went in. Second, it will simplify handling spilling.
With just graph coloring for everything, every time we spill a node, we
have to create new value registers which become new nodes in the graph
and re-run RA. This is worsened by the fact that when writing a value to
a temporary, we need to have an extra register available to load the
write address with a load_const node. With the new scheme, we can ignore
this entirely in the first part and then in the second part we can just
reserve an extra register in sections where we know we have to spill. So
no re-running RA many times, and we can get a good result quickly.

The current implementation does linear scan backwards, so that we can
insert the fake dependencies while allocating and avoid creating any
move nodes at all when we have to split a live range. However, it turns
out that this makes handling schedule_first nodes a bit more
complicated, so it's not clear if that was worth it.

Note:
The commit was originally authored by Connor Abbott <cwabbott@gmail.com>
and was cherry-picked from <mesa/mesa!2315>.
Rebasing was necessary due to changes to BITSET_FOREACH_SET,
see 4413537c
Because some deqp tests pass now, deqp-lima-fails.txt was also changed.
The above changes are

Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7682>
2021-09-01 08:30:57 +00:00
Connor Abbott 3d957b40cc lima: Add a NIR load duplicating pass
and use it with vertex shaders.

Note:
The commit was originally authored by Connor Abbott <cwabbott@gmail.com>
and was cherry-picked from <mesa/mesa!2315>.
Apart from some changes, which were necessary due to rebasing, the following
changes have been added:
clone_intrinsic() was changed to use nir_instr_clone() instead of
doing it manually.
Tests against `src->parent_instr->type != nir_instr_type_phi` have been
inserted, otherwise we may run into a nir validation error.
Intrinsic load_input and load_uniform  are not duplicated, if their source
type is nir_instr_type_load_const.
The above changes are

Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7682>
2021-09-01 08:30:57 +00:00
Marek Olšák ef190b9e15 radeonsi: clean up typecasts in compute_copy_image
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák 34a2c75310 radeonsi: enable DCC stores on gfx10.3 APUs for better performance
There is just one hw bug that we need to handle.

NO_DCC_FB was unused.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák c88a546550 radeonsi: track displayable_dcc_dirty for non-compute shaders
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák 8c845d4cb4 radeonsi: rename DCC_WRITE -> ALLOW_DCC_STORE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák 550f859c53 radeonsi: handle pipe_aligned in compute_expand_fmask
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák 0c39597734 radeonsi: add missing make_CB_shader_coherent for DCC stores into copy_image
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák cb845c53f4 radeonsi: enable DCC stores for clear_render_target on gfx10
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák b648d6fbf8 radeonsi: disable DCC stores on Navi12-14 for displayable DCC to fix corruption
This is a hardware limitation.

Fixes: 1d64a1045e "radeonsi: enable dcc image stores on gfx10+"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Mike Blumenkrantz 0b2b2a4783 zink: remove ZINK_HEAP_HOST_VISIBLE_ANY
this was just the coherent heap but splitting the slabs more to make
suballocating worse

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12659>
2021-09-01 04:24:03 +00:00
Mike Blumenkrantz a923835afc zink: clamp lazy pools to 500 descriptors and allocate more slowly
now that these can get popped without stalling, they can be much smaller
to avoid exploding available memory or address space

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12658>
2021-09-01 04:13:07 +00:00
Mike Blumenkrantz 70f1337f63 zink: use compatible renderpass state in pipeline hash
this massively deduplicates the number of pipelines

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12605>
2021-09-01 03:28:11 +00:00
Mike Blumenkrantz 8dac288c8d zink: track compatible render passes
Two render passes are compatible if their corresponding color, input, resolve, and depth/stencil
attachment references are compatible and if they are otherwise identical except for:
• Initial and final image layout in attachment descriptions
• Load and store operations in attachment descriptions
• Image layout in attachment references

VK 8.2

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12605>
2021-09-01 03:28:11 +00:00