Commit Graph

145564 Commits

Author SHA1 Message Date
Jordan Justen 90feddf38a intel/blorp: Split out surface setup from state emission
Render will use blorp_setup_binding_table and blorp_emit_btp, but
compute will only use blorp_setup_binding_table.

Rework:
 * Use blorp_setup_binding_table, blorp_emit_btp (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Jordan Justen b704c9a75b intel/blorp: Split out ps specific sampler state into a separate function
The compute path will use blorp_emit_sampler_state, whereas the render
path will use blorp_emit_sampler_state_ps.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Jordan Justen dbd4934441 intel/blorp: Add blorp_compile_cs
Reworks:
 * Don't pack params (s-b Jason)
 * Drop nir_remove_dead_variables (s-b Jason)
 * Fix comment s/render target/destination image/ (s-b Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Jordan Justen 998142ea4a intel/blorp: Add subgroup_id input for compute programs
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Jordan Justen 51528aeb60 intel/compiler: Use INTEL_DEBUG=blorp to dump blorp compute shaders
Make INTEL_DEBUG=blorp dump the blorp compute shaders instead using
the general INTEL_DEBUG=cs which is now reserved for actual compute
programs.

Ref: 05933fb0f7 ("intel/compiler: Use INTEL_DEBUG=blorp to dump blorp shaders")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Jordan Justen bd103f9483 intel/blorp: Add brw_blorp_init_cs_prog_key
Reworks:
 * Split out blorp_init_base_prog_key to share with fs/cs key init (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Jordan Justen 794a23ddc7 intel/blorp: Add shader_pipeline to brw_blorp_base_key
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Jordan Justen 5ace2e36cc intel/blorp: Add compute support to BLORP_CREATE_NIR_INPUT
Reworks:
 * Set driver_location (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Jordan Justen a7533a5ad5 intel/blorp: Move most of BLORP_CREATE_NIR_INPUT into a function
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Ed Baker e99278fcf8 frontends/va: Fix test_va_api VAAPIDisplayAttribs tests
Set max_display_attribs to 0 instead of 1 to match
va[Query,Get,Set]DisplayAttributes implementations [1].

If max_display_attribs is greater than 0 libva-utils tests check
vaQueryDisplayAttributes() accordingly [2].

[1] https://gitlab.freedesktop.org/mesa/mesa/-/blob/2de348cdb01e45/src/gallium/frontends/va/display.c#L32
[2] https://github.com/intel/libva-utils/blob/master/test/test_va_api_display_attribs.cpp#L90

Signed-off-by: Ed Baker <edward.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12941>
2021-09-30 17:28:44 +00:00
Gurchetan Singh 9a7d6a110e virgl/drm: explicit context initialization
If the host supports explicit context initialization, try it.
If no capabilitiies associated with virgl are present, return
an error.

Reviewed-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Tested-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7712>
2021-09-30 16:45:12 +00:00
Gurchetan Singh 293c57e12c virgl/drm: query for context init ioctl and supported capset ids
Just add the params to the existing lists.

Reviewed-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Tested-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7712>
2021-09-30 16:45:12 +00:00
Gurchetan Singh bab8e77bb2 drm-uapi: virtgpu_drm.h: context init feature
This change allows creating contexts of depending on set of
context parameters.  The meaning of each of the parameters
is listed below:

1) VIRTGPU_CONTEXT_PARAM_CAPSET_ID

This determines the type of a context based on the capability set
ID.  For example, the current capsets:

VIRTIO_GPU_CAPSET_VIRGL
VIRTIO_GPU_CAPSET_VIRGL2

define a Gallium, TGSI based "virgl" context.  We only need 1 capset
ID per context type, though virgl has two due a bug that has since
been fixed.

The use case is the "gfxstream" rendering library and "venus"
renderer.

gfxstream doesn't do Gallium/TGSI translation and mostly relies on
auto-generated API streaming.  Certain users prefer gfxstream over
virgl for GLES on GLES emulation.  {gfxstream vk}/{venus} are also
required for Vulkan emulation.

The goal is for guest userspace to choose the optimal context type
depending on the situation/hardware.

2) VIRTGPU_CONTEXT_PARAM_NUM_RINGS

This tells the number of independent command rings that the context
will use.  This value may be zero and is inferred to be zero if
VIRTGPU_CONTEXT_PARAM_NUM_RINGS is not passed in.  This is backwards
compatibility for virgl, which has one big giant command ring for all
commands.

The maxiumum number of rings is 32.  In practice, multi-queue or
multi-ring submission is used for powerful dGPUs and virtio-gpu
may not be the best option in that case (see PCI passthrough or
rendernode forwarding).

3) VIRTGPU_CONTEXT_PARAM_POLL_RING_IDX_MASK

This is a mask of ring indices for which the DRM fd is pollable.
For example, if VIRTGPU_CONTEXT_PARAM_NUM_RINGS is 2, then the mask
may be:

[ring idx]  |  [1 << ring_idx] | final mask
-------------------------------------------
    0              1                1
    1              2                3

The "Sommelier" guest Wayland proxy uses this to poll for events
from the host compositor.

Reviewed-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Tested-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7712>
2021-09-30 16:45:12 +00:00
Chia-I Wu e57b80f283 radv: plug leaks in radv_device_init_accel_struct_build_state
Fixes: 0dad88b469 ("radv: Implement device-side BVH building.")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13110>
2021-09-30 15:43:35 +00:00
Boris Brezillon d0637489e8 panvk/ci: Enable blend tests
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:56:38 +02:00
Boris Brezillon 4f484e6d9b panvk: Lower blend operations when needed
The gallium driver makes use of blend shaders, but panvk takes a
slightly different approach. Vulkan drivers are passed the blend
operation at pipeline creation time, which means they know it when
compiling the fragment shader and can lower the blend operation
directly in the fragment shader itself. Doing that simplifies the
pipeline creation since we don't have to deal with blend shaders
anymore.

This might come at a cost for translation layers like Zink though,
since it requires re-compiling the fragment shader every time the
blend operation changes, which we do anyway, since we don't have
a pipeline cache yet. Let's keep things simple for now and revise
things if/when we end up having performance issues.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Suggested-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:56:32 +02:00
Boris Brezillon 9db47ac96e panvk: Fill the blend constants sysval
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:56:23 +02:00
Boris Brezillon 2f68c58767 pan/blend: Allow passing blend constants through a sysval
This is needed to allow lowering blend operations in fragment shaders
when the blend operation uses dynamic blend constants.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:54:42 +02:00
Boris Brezillon 7cd402c9c8 nir/lower_blend: Shrink blended result if needed
Make sure the new and old sources have the same number of components,
otherwise the NIR validation pass complains.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:54:42 +02:00
Boris Brezillon 3e07b8d4f8 nir/lower_blend: Make sure we're not passed scaled formats
SCALED formats are interpreted as floats, but not in the usual [0, 1]
or [-1, 1] range, meaning that the blend lowering logic can't directly
apply to those. Assert that the format being passed is not a scaled
format.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:54:42 +02:00
Boris Brezillon 15b4cab4d5 nir/lower_blend: Don't lower RTs whose format is set to NONE
The caller doesn't necessarily want to lower blend operations on all
render targets since some of them might be supported natively (panvk
will be in that case). Let's just skip RTs that have a format set to
PIPE_FORMAT_NONE to allow that.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:54:42 +02:00
Boris Brezillon 637cd5ac00 nir/lower_blend: Pad src to a 4-component vector
nir_ssa_for_src() is not supposed to pad the src vector if
dst->num_components > src->num_components. Let's pad things explicitly
with nir_pad_vector().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:54:42 +02:00
Boris Brezillon 641bed3103 nir: Make sure src->num_components < dst->num_components in nir_ssa_for_src()
The NIR validation complains if the swizzle accesses a component that's
not present in the source.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:54:42 +02:00
Icecream95 689870e7c4 panfrost: Add ASTC 3D texture format entries
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12814>
2021-09-30 14:26:12 +00:00
Alyssa Rosenzweig e26ffda2b9 panfrost: Encode 3D ASTC dimensions
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12814>
2021-09-30 14:26:12 +00:00
Alyssa Rosenzweig a1c6a15012 panfrost: Use ASTC 2D enums
Rather than manipulating the bits to do the mapping, use a dead simple
switch() with the enum definition.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12814>
2021-09-30 14:26:12 +00:00
Alyssa Rosenzweig 3d28039b3e panfrost: Assert ASTC/AFBC are not used on v4
These are not introduced until v5. The required enums do not exist on
v4. Assert this is so.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12814>
2021-09-30 14:26:12 +00:00
Alyssa Rosenzweig f4f0e30701 panfrost: Add ASTC stretch factor enums
ASTC textures all use a common ASTC format, with the ASTC block
dimension configured with auxiliary bits at the bottom of the payload
pointer. Add the corresponding enum for ASTC 2D and 3D.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12814>
2021-09-30 14:26:12 +00:00
Vadym Shovkoplias 808b426f03 drirc: Set vs_position_always_precise for Assault Android Cactus
A couple of tesselation evaluation shaders lack some precise marks
on its outputs which can lead to different results after optimizations.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5376
Fixes: 09705747d7 ("nir/algebraic: Reassociate fadd into fmul in DPH-like pattern")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13027>
2021-09-30 10:46:39 +00:00
Vadym Shovkoplias 36c241be01 driconf, glsl: Add a vs_position_always_precise option
This is basically the same workaround as in 9b577f2a88 (driconf, glsl: Add a
vs_position_always_invariant option) commit but for tesselation evaluation
shaders. Some applications do not mark outputs as precise in tesselation
evaluation shaders which can lead to different results in case some
optimizations were applied.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Fixes: 09705747d7 ("nir/algebraic: Reassociate fadd into fmul in DPH-like pattern")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13027>
2021-09-30 10:46:39 +00:00
Boris Brezillon 8276a8eb55 panfrost: Move genxml related files to a subdir
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12208>
2021-09-30 10:30:19 +00:00
Boris Brezillon b76420be1f panfrost: Split command stream descriptor definitions per-gen
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12208>
2021-09-30 10:30:19 +00:00
Boris Brezillon 95b37fd21e panfrost: Add a common genxml file so we can share a few definitions
Start with the enums that were manually redefined in
pan_{texture,format}.h and the blend equation descriptors.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12208>
2021-09-30 10:30:19 +00:00
Samuel Pitoiset 27bb80f688 radv: fix selecting the hash when RADV_FORCE_VRS is enabled
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13098>
2021-09-30 10:12:43 +00:00
Samuel Pitoiset 0c88c5cdc4 radv: fix adjusting the frag coord when RADV_FORCE_VRS is enabled
force_vrs was always RADV_FORCE_VRS_NONE at that point and the
hw workaround was never applied.

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13098>
2021-09-30 10:12:43 +00:00
Samuel Pitoiset dca04dae52 radv: remove the LLVM stat about the number of private VGPRs
This doesn't seem really useful.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12999>
2021-09-30 09:51:17 +00:00
Daniel Schürmann 7b04c13a34 aco/ra: don't rewrite affinities for phi operands after register assignment
The effect of doing so is random and not meaningful.

Totals from 52 (0.03% of 150170) affected shaders: (GFX10.3)
CodeSize: 538768 -> 538784 (+0.00%); split: -0.04%, +0.04%
Instrs: 100661 -> 100707 (+0.05%); split: -0.01%, +0.06%
Latency: 1205950 -> 1205768 (-0.02%); split: -0.07%, +0.05%
InvThroughput: 200106 -> 200040 (-0.03%); split: -0.31%, +0.28%
Copies: 5717 -> 5754 (+0.65%); split: -0.17%, +0.82%
Branches: 3153 -> 3162 (+0.29%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann b7af10449b aco/ra: create nested affinities for loop header phis
Totals from 875 (0.58% of 150170) affected shaders: (GFX10.3)
CodeSize: 6084528 -> 6066628 (-0.29%); split: -0.32%, +0.02%
Instrs: 1136497 -> 1133565 (-0.26%); split: -0.28%, +0.02%
Latency: 23355051 -> 22952592 (-1.72%); split: -1.83%, +0.10%
InvThroughput: 13028151 -> 12859628 (-1.29%); split: -1.38%, +0.09%
Copies: 85673 -> 82790 (-3.37%); split: -3.62%, +0.26%
Branches: 25049 -> 25098 (+0.20%); split: -0.08%, +0.28%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann d6bfc95732 aco/ra: create affinities between nested phis
Totals from 17143 (11.42% of 150170) affected shaders: (GFX10.3)
VGPRs: 1138112 -> 1138440 (+0.03%); split: -0.00%, +0.03%
CodeSize: 131235532 -> 131147080 (-0.07%); split: -0.14%, +0.07%
Instrs: 24848044 -> 24775419 (-0.29%); split: -0.32%, +0.02%
Latency: 599031816 -> 596005601 (-0.51%); split: -0.52%, +0.01%
InvThroughput: 152059329 -> 151054105 (-0.66%); split: -0.66%, +0.00%
VClause: 410951 -> 410958 (+0.00%); split: -0.01%, +0.01%
Copies: 1696885 -> 1621908 (-4.42%); split: -4.64%, +0.22%
Branches: 846710 -> 851052 (+0.51%); split: -0.29%, +0.80%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann a2ffdca26a aco/ra: don't set affinities for ssa-repair phis
These have no effect anymore.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann ae5cbd8f3a aco/ra: for phis try to find an operand-matching register earlier
Totals from 3557 (2.37% of 150170) affected shaders: (GFX10.3)
VGPRs: 257976 -> 257984 (+0.00%)
CodeSize: 34296232 -> 34270552 (-0.07%); split: -0.09%, +0.01%
Instrs: 6512289 -> 6506900 (-0.08%); split: -0.10%, +0.01%
Latency: 136376181 -> 136262553 (-0.08%); split: -0.10%, +0.02%
InvThroughput: 33042816 -> 32992849 (-0.15%); split: -0.18%, +0.03%
VClause: 104687 -> 104686 (-0.00%)
SClause: 238657 -> 238663 (+0.00%); split: -0.00%, +0.00%
Copies: 477690 -> 471058 (-1.39%); split: -1.52%, +0.13%
Branches: 223058 -> 224326 (+0.57%); split: -0.02%, +0.59%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann 8995599c80 aco/ra: try more aggressive to assign phi defs the same register
Totals from 4158 (2.77% of 150170) affected shaders: (GFX10.3)
VGPRs: 312008 -> 312000 (-0.00%)
CodeSize: 42902064 -> 42892200 (-0.02%); split: -0.06%, +0.04%
Instrs: 8086443 -> 8084532 (-0.02%); split: -0.07%, +0.05%
Latency: 138551153 -> 138215222 (-0.24%); split: -0.28%, +0.03%
InvThroughput: 39676773 -> 39570850 (-0.27%); split: -0.29%, +0.02%
SClause: 306299 -> 306284 (-0.00%); split: -0.01%, +0.00%
Copies: 552481 -> 553353 (+0.16%); split: -0.75%, +0.91%
Branches: 284381 -> 282409 (-0.69%); split: -0.74%, +0.04%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann 28fe49c35f aco/ra: split register assignment for phis into separate function
No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann 302cb5c900 aco/ra: remove some redundant code
No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann d7cb169819 aco/ra: refactor affinities into assignment struct
This lets us get rid of an unordered_map<>.

No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann 5afcc17f50 aco/ra: fix intersects()
The previous implementation failed when a contained b.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Samuel Pitoiset 9ea0351660 radv: fix missing features for BDA
Only the KHR one is filled by the common code.

Fixes: ec2007d47e ("radv: Use the shared now-in-core feature/prop extension helper functions.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13035>
2021-09-30 08:51:57 +00:00
Jason Ekstrand d2264489ce compiler/clc: grab opencl-c.h from the system path by default
By default we use the header installed opencl-c.h header. But in the
case Mesa is compiled for microsoft clon12 we keep the injected file.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
2021-09-30 07:09:08 +00:00
Jason Ekstrand 8490766f53 compiler/clc: Clean ups
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
2021-09-30 07:09:08 +00:00
Jason Ekstrand 1506ea2ecb Move a bunch of the CLC stuff from src/microsoft to common code
The D3D12-specific stuff isn't useful to have in common code but all the
stuff to invoke clang really should be common.

v2: Rebase (Lionel)

v3: Define a new clc_libclc_new_dxil() entrypoint to create a clc
    context with DXIL nir_options (Jesse)

v4: Fixup meson build (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
2021-09-30 07:09:08 +00:00