Commit Graph

96439 Commits

Author SHA1 Message Date
Matt Turner 4c961a5e79 i965: Add parentheses around usage of macro arguments
Otherwise I cannot use this macro in test_eu_validate.cpp

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2017-10-04 14:08:54 -07:00
Matt Turner 1fcdb1cbea i965: Add GLK, CFL, CNL to test_eu_validate.c 2017-10-04 14:08:54 -07:00
Matt Turner d4c39e9cff i965: Add Atom graphics names to parse_devid_override() 2017-10-04 14:08:54 -07:00
Matt Turner 6db5ec7deb i965: Fix support for disassembling 64-bit integer immediates
The type suffixes were wrong, and the 16 was missing the 0 prefix.

Fixes: 92f787ff86 ("i965: Add support for disassembling 64-bit integer immediates")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2017-10-04 14:08:54 -07:00
Matt Turner 7e88f93469 i965/fs: Rewrite fsign64 to skip the float -> double conversion
... without the float -> double conversion. Low power parts have
additional restrictions when it comes to operating on 64-bit types, and
the instruction used to do the conversion violates one of them:
specifically, the restriction that "Source and Destination horizontal
stride must be aligned to the same qword".

Previously we generated a float and then converted, but we can avoid the
conversion by using the same extract-the-sign-bit + or-in-1.0 algorithm
by directly operating on the high four bytes of each double-precision
component in the result.

In SIMD8 and SIMD16 this cuts one instruction from the implementation,
and more importantly that instruction is the one which violated the
regioning restriction.

Along the way I removed some comments that I did not think helped, and
some code about double comparisons which does not seem to be necessary
today.

This prevents validation failures caught by the new EU validation code
added in later patches.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2017-10-04 14:08:54 -07:00
Matt Turner b541945c20 i965/fs: Unpack count argument to 64-bit shift ops on Atom
64-bit operations on Atom parts have additional restrictions over their
big-core counterparts (validated by later patches).

Specifically, the restriction that "Source and Destination horizontal
stride must be aligned to the same qword" is violated by most shift
operations since NIR uses a 32-bit value as the shift count argument,
and this causes instructions like

   shl(8)          g19<1>Q         g5<4,4,1>Q      g23<4,4,1>UD

where src1 has a 32-bit stride, but the dest and src0 have a 64-bit
stride.

This caused ~4 pixels in the ARB_shader_ballot piglit test
fs-readInvocation-uint.shader_test to be incorrect. Unfortunately no
ARB_gpu_shader_int64 test hit this case because they operate on
uniforms, and their scalar regions are an exception to the restriction.

We work around this by effectively unpacking the shift count, so that we
can read it with a 64-bit stride in the shift instruction. Unfortunately
the unpack (a MOV with a dst stride of 2) is a partial write, and cannot
be copy-propagated or CSE'd.

Bugzilla: https://bugs.freedesktop.org/101984
2017-10-04 14:08:54 -07:00
Matt Turner 2082c32950 i965/fs: Don't apply POW/FDIV workaround on Gen10+
The documentation says it applies only to Gens 8 and 9.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-10-04 14:08:37 -07:00
Matt Turner d407935327 i965: Fix src0 vs src1 typo
A typo caused us to copy src0's reg file to src1 rather than reading
src1's as intended. This caused us to fail to compact instructions like

   mov(8)   g4<1>D    0D              { align1 1Q };

because src1 was set to immediate rather than architecture file. Fixing
this reenables compaction (after the precompact() pass changes the data
types):

   mov(8)   g4<1>UD   0x00000000UD    { align1 1Q compacted };

Fixes: 1cb0a7941b ("i965: Switch to using the logical register types")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-10-04 14:08:24 -07:00
Dave Airlie ad3d98da9f radv: enable tc compatible htile for d32s8 also.
This enables tc compatible htile for stencil surfaces as well.

This gives a 3-5fps boost on Mad Max on high@4k.

It also depends on Bas's tc-compat htile patch.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-04 21:02:23 +01:00
Samuel Pitoiset 844ae722c4 radv: dump SPIRV when a GPU hang is detected
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-04 19:37:08 +02:00
Samuel Pitoiset a2a350a3be radv: dump NIR when a GPU hang is detected
This looks a bit ugly to me, but the existing codepath
is not terribly elegant as well.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-04 19:37:08 +02:00
Marek Olšák 94d800bfa3 ac: silence a warning 2017-10-04 17:00:05 +02:00
Daniel Stone b65d6dafd6 egl/wayland: Don't use dmabuf with no modifiers
The dmabuf interface requires a valid modifier to be sent. If we don't
explicitly get a modifier from the driver, we can't know what to send;
it must be inferred from legacy side-channels (or assumed to linear, if
none exists).

If we have no modifier, then we can only have a single-plane format
anyway, so fall back to the old wl_drm buffer import path.

Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't implement them")
Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reported-by: Andy Furniss <adf.lists@gmail.com>
Cc: Marek Olšák <marek.olsak@amd.com>
2017-10-04 15:17:46 +01:00
Daniel Stone 6273d2f269 egl/wayland: Check queryImage return for wl_buffer
When creating a wl_buffer from a DRIImage, we extract all the DRIImage
information via queryImage. Check whether or not it actually succeeds,
either bailing out if the query was critical, or providing sensible
fallbacks for information which was not available in older DRIImage
versions.

Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't implement them")
Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reported-by: Andy Furniss <adf.lists@gmail.com>
Cc: Marek Olšák <marek.olsak@amd.com>
2017-10-04 15:17:46 +01:00
Eric Engestrom d246aa3a0d travis: move include path from $CC to $CFLAGS
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-04 15:02:37 +01:00
Tobias Klausmann 80bfff5c4f wayland-egl: adds CFLAGS for wayland.egl.h include
Starting with commit ab0589c6ed ("wayland-egl: remove no longer needed
wayland-client dependency") the wayland-egl.h include was missing leading to a
build failure:

  CC       wayland-egl.lo
wayland-egl.c:33:10: fatal error: wayland-egl.h: No such file or directory
 #include "wayland-egl.h"
          ^~~~~~~~~~~~~~~

Strictly speaking we should be checking for wayland-egl in configure and
propagating its CFLAGS here.

Yet again, the current wayland-egl split is bonkers as the Wayland repo
provides single header, no pkg-config file or library.

That will be resolved at a later stage, but in the meanwhile fix the
build.

Fixes: ab0589c6ed ("wayland-egl: remove no longer needed wayland-client
dependency")
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil Velikov: add some text about CFLAGS and current wayland-egl situation]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-04 14:25:06 +01:00
Emil Velikov fd404e3c17 automake: add texcompress_s3tc_tmp.h to the sources list
Otherwise it will be missing from the tarball.

Fixes: f7daa737d1 ("mesa: Combine libtxc_dxtn sources into
texcompress_s3tc_tmp.h")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-04 14:21:40 +01:00
Leo Liu 409491e778 st/va: add RGB support to vlVaPutSurface
Tested-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-10-04 09:22:33 -04:00
Leo Liu 0fa950ecd3 st/va: don't re-allocate interlaced buffer with pakced format
It caused corruption, when vlVaPutImage putting raw data to the fields

v2: add RGB formats since it got uploaded here as well

Cc: mesa-stable@lists.freedesktop.org
Cc: Andy Furniss <adf.lists@gmail.com>
Tested-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-10-04 09:22:33 -04:00
Leo Liu 327480d10f st/vdpau: don't re-allocate interlaced buffer with packed YUV format
It caused corruption, when vlVdpVideoSurfacePutBitsYCbCr putting YUV to the fields

Cc: mesa-stable@lists.freedesktop.org
Cc: Andy Furniss <adf.lists@gmail.com>
Tested-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-10-04 09:22:33 -04:00
Bas Nieuwenhuizen ae61fe4982 radv: Implement TC compatible HTILE.
The situations where we enable it are quite limitied, but it works,
even for madmax, so lets just enable it.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-04 09:19:26 +02:00
Dave Airlie 4e93d6baae radv: emit fmuladd instead of fma to llvm.
For Vulkan SPIR-V the spec states
fma() Inherited from OpFMul followed by OpFAdd.

Matt says the backend will do the right thing depending on the
hardware being compiled for, if you use the fmuladd intrinsic.

Using the Mad Max pts test, on high settings at 4K:
CHP: 55->60
HGDD: 46->50
LM: 55->60
No change on Stronghold.

Thanks to Feral for spending the time to track this down.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-04 06:22:44 +01:00
Tapani Pälli b2dce27373 android: fix build issues with brw_nir_trig_workarounds.c
Fixes: 848da66222 ("intel: use a flag instead of setting PYTHONPATH")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-04 07:39:05 +03:00
Lionel Landwerlin d3acc240d0 intel: compiler: vec4: add missing default 0 lod
We set a similar default value for LOD in the fs backend for TXS/TXL.
Without this we end up generating invalid MOV with a null src.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-10-03 22:50:46 +01:00
Jason Ekstrand 8733567e05 anv: Remove base_vertex/instance from push_constants
This is just legacy cruft.  We don't push these values; we pass them in
as vertex attributes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-10-03 13:41:00 -07:00
Brian Paul e4c7a2ab68 util: include string.h in u_string.h
To fix MinGW compiler warning about missing strlen() prototype.
Not sure how I missed this when fixing the malloc() / stdlib.h issue.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-10-03 14:33:00 -06:00
Brian Paul 33122e8a3d llvmpipe: silence 'variable may be used uninitialized' warnings
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-10-03 14:33:00 -06:00
Brian Paul 42eb3052c3 mesa: silence 'variable may be used uninitialized' warning in teximage.c
Found with MinGW optimized build.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-10-03 14:32:59 -06:00
Brian Paul fed856478c mesa: silence 'variable may be used uninitialized' warning in bufferobj.c
Found with MinGW optimized build.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-10-03 14:32:59 -06:00
Brian Paul 980fe46d72 svga: wrap long comments in svga_tgsi_vgpu10.c
Trivial.
2017-10-03 12:07:05 -06:00
Brian Paul 362fb05b65 svga: tweak pre-VGPU10 rasterization offsets
It seems there's no perfect x/y biases for line drawing to satisfy all
applications.  Depending on the biases, either real apps produce results
similar to VGPU10 while Piglit's gl-1.0-ortho-pos fails, or vice versa.

Let's lean toward real applications (Solidworks, SolidEdge, Google Earth)
over Piglit.

Using (-0.5, -0.5) for points, lines and triangles, seems to generally
work well.

We don't seem to have these issues with VGPU10.

Tested with Piglit and CAD-oriented apitraces.  See VMware bugs 1775498
and 1905053.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-10-03 12:07:05 -06:00
Brian Paul 3e39abf6a0 svga: if we get nr_samples==1, store nr_samples=0
We need to be more careful not to treat nr_samples=1 as an msaa surface.
This patch prevents us from errantly declaring an MSAA shader resource
with 1 sample.

No Piglit regressions, fixes the above-described errors.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-10-03 12:07:05 -06:00
Charmaine Lee 3c71c42827 svga: emit sampler constants only if sampler view exists
It is possible to have holes in the shader emitter's sampler_target array.
0 sampler_target does not necessarily mean there is no sampler view
specified since texture buffer target has the value 0.
With this patch, a sampler_view array is added to the shader emitter structure
to specify if there is a sampler view for each texture unit. Only if there
is a sampler view, we will emit constant for texcoord scale factor or texture
buffer size for that sampler view.

Fixes a rendering issue with Turbine after commit 1020e960440.

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-10-03 12:07:05 -06:00
Brian Paul b7c08e5081 svga: fix incorrect case in svga_typeless_format()
For the case of SVGA3D_X32_G8X24_UINT we incorrectly returned
SVGA3D_R32_FLOAT_X8X24.  We should return SVGA3D_R32G8X24_TYPELESS.

Note that we never actually use SVGA3D_X32_G8X24_UINT so this has
no impact.

No Piglit regressions.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-10-03 12:07:05 -06:00
Brian Paul cbe72ae598 svga: add typeless switch cases in svga_typeless_format()
We sometimes pass typeless formats to this function.  By adding switch
cases we avoid the "Unexpected format XXX in svga_typeless_format"
warning messages.  No functional change.

No Piglit regressions, no above-mentioned warning messages.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-10-03 12:07:05 -06:00
Neha Bhende 9a7d42b71c svga: Allow sRGB format with PIPE_BIND_DISPLAY_TARGET binding flag on vgpu10.
This patch allows to use sRGB formats for DISPLAY_TARGET on vgpu10.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-10-03 12:07:05 -06:00
Wladimir J. van der Laan df6b320a83 etnaviv: Set up unknown GC3000 states
Set up new states that the blob started setting for GC3000 consistently.

This makes sure that when another test or driver leaves the GPU in
unpredictable state, these states are set up correctly for our
rendering.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-10-03 19:52:07 +02:00
Wladimir J. van der Laan a2132fbd79 etnaviv: Fix point sprite rendering on GC3000
Setting PA_VIEWPORT_UNK state correctly is necessary to make point sprite
rendering on GC3000 work.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-10-03 19:51:52 +02:00
Wladimir J. van der Laan ec254f4bfa etnaviv: Add support for DP2 instruction
A two-component dot product instruction is supported with HALTI2, use it
on hardware that supports it.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-10-03 19:49:47 +02:00
Wladimir J. van der Laan 80f608b530 etnaviv: Support opcodes with bit 6 set in assembler
Support opcodes with bit 6 set in assembler, and assert that only ops
0x00..0x7f are used.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-10-03 19:49:38 +02:00
Dylan Baker df82012b2c travis: add meson build for vulkan drivers.
v2: - use -isystem`pwd` instead of cp to include fake linux header
      (Eric E., Emil)

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-03 10:02:08 -07:00
Dylan Baker 7a5a986ddd meson: convert gtest to an internal dependency
In truth gtest is an external dependency that upstream expects you to
"vendor" into your own tree. As such, it makes sense to treat it more
like a dependency than an internal library, and collect it's
requirements together in a dependency object.

v2: - include with -isystem instead of setting compiler args (Eric)

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-03 10:02:08 -07:00
Dylan Baker 052c0d5eda meson: set C++ standard to C++11
RadeonSI requires C++11, clover requires C++11, LLVM requires it, so
llvmpipe may require it, and that covers most of the C++ code in mesa.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-03 10:02:04 -07:00
Dylan Baker af867d72c6 meson: add window system deps to intel vulkan common
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-03 10:01:45 -07:00
Dylan Baker cc4f587307 meson: look for libelf as a library if there is no pkgconfig
Required for older versions of libelf that don't have a pkgconfig file.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-03 10:01:45 -07:00
Gurchetan Singh 9d9a46d4ef egl/surfaceless: Use KMS swrast fallback
The kms_swrast extension is an actively developed software fallback,
and platform_surfaceless can use it if there are no available
hardware drivers.

v2: Split into 2 patches, use booleans, check LIBGL_ALWAYS_SOFTWARE,
    and modify the eglLog level (Emil, Eric, Tomasz).

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-03 17:56:15 +01:00
Gurchetan Singh 540c804297 egl/surfaceless: add probe device helper function
This will help us initialize a software driver, if it's needed
or requested.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-03 17:56:15 +01:00
George Kyriazis a8e4a0f609 gallium/u_tests: fix ifdef for sync_file fences
include libsync.h only when libdrm is compiled in

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-03 11:50:48 -05:00
Brian Paul 2d4b57fc3e util: include stdlib.h in u_string.h to silence MinGW warning
Otherwise we don't get a prototype for malloc().

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-03 10:15:03 +01:00
Kenneth Graunke bf15dc7a1b intel: Always set Cube Face Enables for all surfaces.
These shouldn't matter for non-cubes, and we always enable them all
for cubes, so we may as well set them all the time.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-03 00:06:34 -07:00