Commit Graph

109720 Commits

Author SHA1 Message Date
Alyssa Rosenzweig b8739c24ee panfrost/midgard: Add ult/ule ops
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:36:09 +00:00
Alyssa Rosenzweig f277bd3c22 panfrost: Stub out ES3 caps/callbacks
Although this is not functional (and the command stream side is not
aiming for ES3 right now), this is enough to run dEQP-GLES3 shader
tests with the version override directive; this is useful, as some ES3
shader feature can occur in ES2 class shaders due to lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:58 +00:00
Alyssa Rosenzweig 89989e653e panfrost/midgard: Cleanup midgard_nir_algebraic.py
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:37 +00:00
Alyssa Rosenzweig effe6fb08d panfrost/midgard: Lower source modifiers for ints
On Midgard, float ops support standard source modifiers (abs/neg) and
destination modifiers (sat/pos/round). Integer ops do not support these,
however. To cope, we use native NIR source modifiers for floats, but
lower them away to iabs/ineg for integers, implementing those ops
simultaneously to avoid regressions.

Fixes the integer tests in
dEQP-GLES2.functional.shaders.operator.unary_operator.minus.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:36 +00:00
Alyssa Rosenzweig 3208c9d9a2 panfrost/midgard: Implement b2i; improve b2f/f2b
Fixes
dEQP-GLES2.functional.shaders.conversions.scalar_to_scalar.bool_to_int_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:27 +00:00
Alyssa Rosenzweig 5b95fef493 panfrost/midgard: Lower i2b32
Fixes
dEQP-GLES2.functional.shader.conversions.scalar_to_scalar.int_to_bool_vertex

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:26 +00:00
Alyssa Rosenzweig ae43b8faa7 panfrost/midgard: Lower f2b32 to fne
Fixes
dEQP-GLES2.functional.shaders.swizzles.vector_swizzles.mediump_bvec2_x_vertex

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:24 +00:00
Alyssa Rosenzweig 3fb884259b panfrost/midgard: Lower bool_to_int32
Fixes dEQP-GLES2.functional.shaders.linkage.varying_type_vec2 (among
many others).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:22 +00:00
Alyssa Rosenzweig 53664108c2 panfrost/midgard: Map more bany/ball opcodes
Some of these are not yet fully functional due to related bugs, but this
the correct op mapping. The native ball/bany opcodes act on vec4's
unconditionally. That said, both ball and bany have the nice property
that duplicating an argument does not affect their output, so the
default "hanging swizzles" allow us to implement 2/3-component opcodes
correctly, implicitly lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:20 +00:00
Alyssa Rosenzweig 88b2a6b451 panfrost/midgard: Add more ball/bany, iabs ops
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:18 +00:00
Alyssa Rosenzweig 72cd677bac panfrost/midgard: Schedule ball/bany to vectors
Though they output scalars, they need a vector unit to make sense.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:17 +00:00
Alyssa Rosenzweig 89fdbb6707 panfrost/midgard: Add fcsel_i opcode
Whereas a normal fcsel acts on a boolean input in r31.w, the fcsel_i
variant acts on an integer input in r31.w, which can be preloaded with
an instruction like imov (with the appropriate negate flag on the
source).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:15 +00:00
Alyssa Rosenzweig 121417ef1d panfrost: Implement scissor test
This preliminary implementation should handle some basic cases. Future
work should scissor the FRAGMENT job as well for efficiency.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:14 +00:00
Alyssa Rosenzweig bd9446e719 panfrost: Fix viewports
Our viewport code hardcoded a number of wrong assumptions, which sort of
sometimes worked but was definitely wrong (and broke most of dEQP). This
corrects the logic, accounting for flipped-Y framebuffers, which
fixes... most of dEQP.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:10 +00:00
Alyssa Rosenzweig 9da4603fb6 panfrost/midgard: Fix b2f32 swizzle for vectors
Fixes issues in most of dEQP-GLES2.functional.shaders.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-26 23:35:08 +00:00
Dave Airlie e77013fb7f softpipe: fix clears to only clear specified color buffers.
This fixes piglit clearbuffer-mixed-format

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-27 07:53:32 +10:00
Dave Airlie 7f7c9425a8 draw/vs: partly fix basevertex/vertex id
This gets the basevertex from the draw depending on whether
it's an indexed or non-indexed draw.

We still fail a transform feedback test for vertex id, as
the vertex id actually an index id, and isn't getting translated
properly to a vertex id, suggestions on how/where to fix that welcome.

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-27 07:52:28 +10:00
Nicolai Hähnle e16ac33f37 amd/surface: provide firstMipIdInTail for metadata surface calculations
This field was added in a recent addrlib update, and while there
currently seems to be no issue with skipping it, we will have to
set it correctly in the future.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-03-26 10:00:55 +01:00
Bas Nieuwenhuizen 82075e3c42 ac/nir: Return frag_coord as integer.
To preserve the invariant that nir ssa defs are integers or pointers
in LLVM.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-03-26 09:41:15 +01:00
Kristian H. Kristensen c7c432738a freedreno/ir3: Fix operand order for DSX/DSY
Most cat5 instructions are constructed using ir3_SAM, which uses
regs[1] for the (sampler, tex) src. Not DSX/DSY though, so we look up
src1 and src2 differently for those two.

Fixes: 1dffb089 ("freedreno/ir3: fix sam.s2en encoding")
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-03-25 18:36:48 -07:00
Kristian H. Kristensen a752422bd4 freedreno/ir3: Track whether shader needs derivatives
In 1088b788 ("freedreno/ir3: find # of samplers from uniform vars") we
started counting number of samplers based on the uniform vars instead
of number of cat5 instructions.  We used the number of samplers to
determine whether to enable derivatives, but when we only use
derivatives and no samplers, that now breaks.  Track whether we need
derivatives explicitly and use that to enable the state.

Fixes: 1088b788 ("freedreno/ir3: find # of samplers from uniform vars")
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-03-25 18:36:48 -07:00
Andre Heider 12f11e6fe6 st/nine: enable csmt per default on iris
iris is thread safe, enable csmt for a ~5% performace boost.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
2019-03-25 22:21:19 +01:00
Jason Ekstrand 8ed583fe52 spirv: Handle the NonUniformEXT decoration 2019-03-25 16:12:09 -05:00
Jason Ekstrand e50ab2c0f2 nir: Add access flags to deref and SSBO atomics
We will need them for a new ACCESS_NON_UNIFORM flag that's about to be
added in the next commit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-25 16:12:09 -05:00
Jason Ekstrand 40074ebf74 nir: Add texture sources and intrinsics for bindless
On Intel, we have both bindless and bindful and we'd like to use them at
the same time if we can so we need to be able to distinguish at the NIR
level between the two.  This also fixes nir_lower_tex to properly handle
bindless in its tex_texture_size and get_texture_lod helpers.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-25 16:12:09 -05:00
Danylo Piliaiev e0db0c74b9 intel/fs: Make alpha test work with MRT and sample mask
Fix the order of src0_alpha and sample mask in fb payload.
From SKL PRM Volume 7, "Data Payload Register Order
for Render Target Write Messages":
 Type   S0A  oM  sZ  oS  M2     M3       M4
 SIMD8   1   1   0   0   s0A    oM       R
 SIMD16  1   1   0   0   1/0s0A 3/2s0A   oM

It also fixes working of alpha to coverage with sample mask
on GEN6 since now they are in correct order.

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by:  Francisco Jerez <currojerez@riseup.net>
2019-03-25 13:54:55 -07:00
Danylo Piliaiev c8abe03f3b i965,iris,anv: Make alpha to coverage work with sample mask
From "Alpha Coverage" section of SKL PRM Volume 7:
 "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
  hardware, regardless of the state setting for this feature."

From OpenGL spec 4.6, "15.2 Shader Execution":
 "The built-in integer array gl_SampleMask can be used to change
 the sample coverage for a fragment from within the shader."

From OpenGL spec 4.6, "17.3.1 Alpha To Coverage":
 "If SAMPLE_ALPHA_TO_COVERAGE is enabled, a temporary coverage value
  is generated where each bit is determined by the alpha value at the
  corresponding sample location. The temporary coverage value is then
  ANDed with the fragment coverage value to generate a new fragment
  coverage value."

Similar wording could be found in Vulkan spec 1.1.100
"25.6. Multisample Coverage"

Thus we need to compute alpha to coverage dithering manually in shader
and replace sample mask store with the bitwise-AND of sample mask and
alpha to coverage dithering.

The following formula is used to compute final sample mask:
  m = int(16.0 * clamp(src0_alpha, 0.0, 1.0))
  dither_mask = 0x1111 * ((0xfea80 >> (m & ~3)) & 0xf) |
     0x0808 * (m & 2) | 0x0100 * (m & 1)
  sample_mask = sample_mask & dither_mask
Credits to Francisco Jerez <currojerez@riseup.net> for creating it.

It gives a number of ones proportional to the alpha for 2, 4, 8 or 16
least significant bits of the result.

GEN6 hardware does not have issue with simultaneous usage of sample mask
and alpha to coverage however due to the wrong sending order of oMask
and src0_alpha it is still affected by it.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109743

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2019-03-25 13:54:55 -07:00
Jason Ekstrand 3bd5457641 nir: Add a lowering pass for non-uniform resource access
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-25 15:00:36 -05:00
Jason Ekstrand 39da1deb49 nir/lower_io: Add a bounds-checked 64-bit global address format
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-25 14:40:54 -05:00
Dave Airlie 551950cacd draw/gs: fix point size outputs from geometry shader.
If the geom shader emits a point size we failed to find it here,
use the correct API to look it up.

Fixes:
tests/spec/glsl-1.50/execution/geometry/point-size-out.shader_test

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-26 05:17:06 +10:00
Dave Airlie d3836510d2 draw: bail instead of assert on instance count (v2)
With indirect rendering it's fine to set the instance count
parameter to 0, and expect the rendering to be ignored.

Fixes assert in KHR-GLES31.core.compute_shader.pipeline-gen-draw-commands
on softpipe

v2: return earlier before changing fpstate

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-26 05:16:56 +10:00
Leo Liu 382401aab7 vl/dri3: remove the wait before getting back buffer
The wait here is unnecessary since we got a pool of back buffers,
and the wait for swap buffer will happen before the present pixmap,
at the same time the previous back buffer will be put back to pool
for reuse after the check for PresentIdleNotify event

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2019-03-25 12:20:31 -04:00
Iago Toral Quiroga 763c8aabed compiler/nir: add lowering for 16-bit ldexp
v2 (Topi):
 - Make bit-size handling order be 16-bit, 32-bit, 64-bit
 - Clamp lower exponent range at -28 instead of -30.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-25 16:08:25 +01:00
Iago Toral Quiroga 3766334923 compiler/nir: add lowering for 16-bit flrp
And enable it on Intel.

v2:
 - Squash the change to enable it on Intel (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-25 16:08:25 +01:00
Iago Toral Quiroga ca31df6f1f compiler/nir: add lowering option for 16-bit fmod
And enable it on Intel.

v2:
 - Squash the change to enable this lowering on Intel (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-25 16:08:25 +01:00
Brian Paul 08d97aadd1 st/mesa: fix texture deletion context mix-up issues (v2)
When we destroy a context, we need to temporarily make that context
the current one for the thread.

That's because during context tear-down we make many calls to
_mesa_reference_texobj(&texObj, NULL).  Note there's no context
parameter.  If the texture's refcount goes to zero and we need to
delete it, we use the thread's current context.  But if that context
isn't the context we're tearing down, we get into trouble when
deallocating sampler views.  See patch 593e36f956 ("st/mesa:
implement "zombie" sampler views (v2)") for background information.

Also, we need to release any sampler views attached to the fallback
textures.

Fixes a crash on exit with a glretrace of the Nobel Clinician
application.

v2: at end of st_destroy_context(), check if save_ctx == ctx and
unbind the context if so.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-03-25 06:57:57 -06:00
Brian Paul d13167cd21 nir: fix a few signed/unsigned comparison warnings
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-25 06:51:31 -06:00
Kishore Kadiyala e1d8057160 android: static link with libexpat with Android O+
In Android O, MESA needs to statically link libexpat so that
it's in same VNDK namespace.

v2: apply change also to anv driver (Tapani)
v3: use += in anv change (Eric Engestrom)

Change-Id: I82b0be5c817c21e734dfdf5bfb6a9aa1d414ab33
Signed-off-by: Kishore Kadiyala <kishore.kadiyala@intel.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-25 10:11:57 +02:00
Samuel Iglesias Gonsálvez 01cf390035 radv: write availability status vkGetQueryPoolResults() when the data is not available
If VK_QUERY_RESULT_WITH_AVAILABILY_BIT is set and
VK_QUERY_RESULT_WAIT_BIT and VK_QUERY_RESULT_PARTIAL_BIT are both not
set, we need return to VK_NOT_READY only and set the availability
status field for each query.

From Vulkan spec:

"If VK_QUERY_RESULT_WAIT_BIT and VK_QUERY_RESULT_PARTIAL_BIT are both
not set then no result values are written to pData for queries that are
in the unavailable state at the time of the call, and
vkGetQueryPoolResults returns VK_NOT_READY. However, availability state
is still written to pData for those queries if
VK_QUERY_RESULT_WITH_AVAILABILITY_BIT is set."

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-03-25 08:21:22 +01:00
Samuel Iglesias Gonsálvez cb3ea50ec2 radv: don't overwrite results in VkGetQueryPoolResults() when queries are not available
If the query is not available and VK_QUERY_RESULT_WAIT_BIT and
VK_QUERY_RESULT_PARTIAL_BIT are both not set, the spec doesn't
allow to modify its result.

From Vulkan spec:

"If VK_QUERY_RESULT_WAIT_BIT and VK_QUERY_RESULT_PARTIAL_BIT are
both not set then no result values are written to pData for queries
that are in the unavailable state at the time of the call, and
vkGetQueryPoolResults returns VK_NOT_READY. However, availability state
is still written to pData for those queries
if VK_QUERY_RESULT_WITH_AVAILABILITY_BIT is set."

v2:
- Move VK_NOT_READY change to next patch (Samuel Pitoiset)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-03-25 08:21:22 +01:00
Tapani Pälli 2c240a5216 st/mesa: fix warnings about implicit conversion on enumeration type
These enums match but compiler warns about implicit conversion.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-03-25 07:44:27 +02:00
Tapani Pälli ec12316489 st/mesa: fix compilation warning on storage_flags_to_buffer_flags
(warning: 'const' type qualifier on return type has no effect)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-03-25 07:44:05 +02:00
Dave Airlie 9417793fb1 nir/split_vars: fixup some more explicit_stride related issues.
With vkpipelinedb Samuel discovered a regression since we stopped
stripping types at the spir-v level.

This adds a check to the var splitting for the case where it
asserts the type hasn't changed, when it has just created a bare
type, and it's different than the original type which has an explicit
stride.

This also removes a pointless assert that also triggers.

Fixes: 3b3653c4cf (nir/spirv: don't use bare types, remove assert in split vars for testing)

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-25 13:57:16 +10:00
Caio Marcelo de Oliveira Filho 9d0ae777dd spirv: Use interface type for block and buffer block
Also handle GLSL_TYPE_INTERFACE the same way we do GLSL_TYPE_STRUCT in
various places.  Motivated by ARB_gl_spirv work, that will take
advantage of the interface types when handling NIR coming from SPIR-V.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-23 10:22:39 -07:00
Caio Marcelo de Oliveira Filho fb024f5e72 intel/compiler: handle GLSL_TYPE_INTERFACE as GLSL_TYPE_STRUCT
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-23 10:22:39 -07:00
Caio Marcelo de Oliveira Filho 15012077bc spirv: Add an execution environment to the options
Also updates gl_spirv to pick the right one.  At the moment nothing
uses it, but upcoming functionality part of ARB_gl_spirv will use it,
and we also later can be more assertful when handling certain features
for each of the execution environments.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
2019-03-23 09:29:21 -07:00
Eric Anholt dacb11a585 egl: Add a 565 pbuffer-only EGL config under X11.
The CTS requires a 565-no-depth-no-stencil (meaning d/s not-required, not
not-present) config for ES 3.0, but at depth 24 of X11 we wouldn't do so.
We can satisfy that bad requirement using a pbuffer-only visual with
whatever other buffers the driver happens to have given us.

I've tried to raise this as an absurd requirement with Khronos and made no
progress.

v2: Make sure it's single sample, no depth, no stencil.  Comment typo fix

Reviewed-by: Adam Jackson <ajax@redhat.com>
2019-03-22 15:22:40 -07:00
Caio Marcelo de Oliveira Filho e5830e1132 nir: Handle array-deref-of-vector case in loop analysis
SPIR-V can produce those for SSBO and UBO access.  Found when testing
the ARB_gl_spirv series.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-03-22 13:50:39 -07:00
Rob Clark cdd90a7502 docs: update freedreno status
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-22 16:39:14 -04:00
Rob Clark 6fd5a7ff8c freedreno: add ESSL cap
Report 320 for a6xx, which isn't *quite* true (no geom/tess, in
particular), but other caps keep the reported GL and GLSL versions
correct (3.1 / 3.10 es).  But reporting 320 will switch on
EXT_gpu_shader5, which is the goal.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-22 16:39:14 -04:00