Commit Graph

33075 Commits

Author SHA1 Message Date
Dylan Baker 831d2fb012 meson: sort gallium drivers after winsys
This is a requirement of the next patch. Since meson does not have
forward declarations, and we're going to define the driver dependencies
in the drivers folder they need to be after the winsys so that the
winsys libs are defined first.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-12-04 14:35:31 -08:00
Dylan Baker 383cdaf990 meson: Combine gallium target subdirs
So that state trackers, targets, and special winsys requirements are all
in a single if statement. This is a cosmetic only cleanup with no
functional changes.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-12-04 14:35:03 -08:00
Rob Clark 1ec1ae47f7 freedreno: mark stencil buffer valid too in case of z32x24s8
The separate stencil buffer was not also getting marked as valid if
written by a draw/clear, resulting in gmem2mem getting skipped.  Move
this into fd_batch_resource_used() which also handles the separate
stencil case.

Also fix restore_buffers typo.

Fixes: 4ab6ab8036 freedreno: avoid mem2gmem for invalidated buffers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-04 11:50:45 -05:00
Rob Clark e90f1a26c3 freedreno: remove use of u_transfer
Freedreno doesn't treat buffers and images differently, so it's use was
kind of pointless.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-04 11:50:45 -05:00
Eric Engestrom 7c3f958d23 freedreno: add -Wno-packed-bitfield-compat for meson build
Otherwise huge amount of spam from instr-a2xx.h.. gcc has no way to know
that freedreno was never built with such an old gcc version to care
about the bugs in old gcc ;-)

Reported-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
[added commit message]
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-04 11:50:45 -05:00
Pierre Moreau 9bee12160b nvc0/ir: Properly lower 64-bit shifts when the shift value is >32
Fixes: 61d7676df7 "nvc0/ir: add support for 64-bit shift lowering on SM20/SM30"

Fixes fs-shift-scalar-by-scalar.shader_test from piglit for the current
set-up:

uniform int64_t ival -0x7dfcfefbdf6536ff # bit pattern: 0x82030104209ac901
uniform uint64_t uval 0x1400000085010203
uniform int shl 36
uniform int shr 36
uniform int64_t iexpected_shl 0x09ac901000000000
uniform int64_t iexpected_shr -0x7dfcff0 # bit pattern: 0xfffffffff8203010
uniform uint64_t uexpected_shl 0x5010203000000000
uniform uint64_t uexpected_shr 0x0000000001400000
draw rect ortho 12 0 4 4

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-12-04 01:03:47 -05:00
Timothy Arceri 27888977c1 st/glsl_to_nir/radeonsi: enable gs support for nir backend
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-04 12:52:19 +11:00
Timothy Arceri ccd1810bba ac: add si_nir_load_input_gs() to the abi
V2: make use of driver_location and don't expose NIR to the ABI.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-04 12:52:19 +11:00
Timothy Arceri 4184e7c417 radeonsi: create si_llvm_load_input_gs()
This creates a common function that can be shared by the tgsi
and nir backends.

v2: use LLVMBuildBitCast() directly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-04 12:52:18 +11:00
Timothy Arceri c4c8df94bd radeonsi: pass llvm type to lds_load()
v2: use LLVMBuildBitCast() directly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-04 12:52:18 +11:00
Timothy Arceri 650126f3e0 radeonsi: add llvm_type_is_64bit() helper
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-04 12:52:18 +11:00
Timothy Arceri 7ef1e42c14 radeonsi: pass llvm type to si_llvm_emit_fetch_64bit()
v2: use LLVMBuildBitCast() directly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-04 12:52:18 +11:00
Timothy Arceri e51ecbe980 radeonsi: add nir support for gs epilogue
v2: add emit_gs_epilogue() helper function to reduce duplication.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-04 12:52:18 +11:00
Timothy Arceri 73918b3172 radeonsi: add nir support for es epilogue
v2: make use of existing si_tgsi_emit_epilogue()

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-04 12:52:18 +11:00
Timothy Arceri 204f547852 radeonsi: add nir support for ls epilogue
v2: make use of existing si_tgsi_emit_epilogue()

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-04 12:52:18 +11:00
Timothy Arceri 6648bd68fd st/glsl_to_nir: enable NIR link time opts
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-12-04 09:10:30 +11:00
Timothy Arceri c16a0e11d3 radeonsi/nir: add support for packed inputs
Because NIR can create non vec4 variables when implementing component
packing we need to make sure not to reprocess the same slot again.

Also we can drop the fs_attr_idx counter and just use driver_location.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-12-04 09:10:30 +11:00
Rob Clark 11efe42a73 freedreno/ir3: relax barriers
Instructions with no barrier_class can move wrt. an EVERYTHING barrier.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-03 14:17:41 -05:00
Rob Clark 48eef0c182 freedreno/ir3: all mem instructions have WAR hazzard
It isn't just load instructions that have write-after-read hazzard.

Fixes stk gaussian blur compute shaders.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-03 14:17:41 -05:00
Rob Clark e6c6495d3a freedreno: add debug option to force emulated indirect
Useful mostly for debugging indirect draw.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-03 14:17:41 -05:00
Rob Clark f93f2f7b1e freedreno: also mark draw-indirect buffer as read
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-03 14:17:41 -05:00
Rob Clark 4b1d0d2844 freedreno: small cleanups
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-03 14:17:41 -05:00
Rob Clark 91730fb0ff freedreno: avoid unneccessary batch flush
In some cases we can end up trying to add a write dependency on ourself,
which shouldn't trigger a flush.

Avoids an extra couple flushes per from in stk.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-03 14:17:41 -05:00
Rob Clark 4ab6ab8036 freedreno: avoid mem2gmem for invalidated buffers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-03 14:17:41 -05:00
Rob Clark 2fcf6faa06 freedreno: deferred flush support
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-03 14:17:41 -05:00
Rob Clark 15ebf387fc freedreno: rework fence tracking
ctx->last_fence isn't such a terribly clever idea, if batches can be
flushed out of order.  Instead, each batch now holds a fence, which is
created before the batch is flushed (useful for next patch), that later
gets populated after the batch is actually flushed.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-03 14:17:40 -05:00
Rob Clark deb57fb237 freedreno: proper locking for iterating dependent batches
In transfer_map(), when we need to flush batches that read from a
resource, we should be holding screen->lock to guard against race
conditions.  Somehow deferred flush seems to make this existing
race more obvious.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-03 14:17:40 -05:00
Rob Clark ef6313ffd3 freedreno/a5xx: correct max_indicies for indirect draws
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-03 14:17:40 -05:00
Eric Anholt 0ed952c7e9 broadcom/vc4: Use a single-entry cached last_hindex value.
Since almost all BOs will be in one CL at a time, this cache will almost
always hit except for the first usage of the BO in each CL.

This didn't show up as statistically significant on the minetest trace
(n=340), but if I lop off the throttled lobe of the bimodal distribution,
it very clearly does (0.74731% +/- 0.162093%, n=269).
2017-12-01 15:37:28 -08:00
Eric Anholt 230e646a40 broadcom/vc4: Decompose single QUADs to a TRIANGLE_FAN.
No significant difference in the minetest replay, but it should reduce
overhead by not requiring that we write quad indices to index buffers that
we repeatedly re-upload (and making the draw packet smaller, as well).

Over the course of the series the actual game seems to be up by 1-2 fps.
2017-12-01 15:37:28 -08:00
Eric Anholt 5167367050 broadcom/vc4: Skip emitting redundant VC4_PACKET_GEM_HANDLES.
Now that there's only one user of it, it's pretty obvious how to avoid
emitting redundant ones.  This should save a bunch of kernel validation
overhead.

No statistically sigificant difference on the minetest trace I was looking
at (n=169), but the maximum FPS is up by .3%
2017-12-01 15:37:28 -08:00
Eric Anholt 842b05d6ad broadcom/vc4: Simplify the relocation handling for index buffers.
Originally there was CL code for handling various relocations back when I
had relocs for the TSDA/TA buffers.  Now that the kernel handles those
entirely on its own, I can inline that code into the one place using it.
2017-12-01 15:37:28 -08:00
Eric Anholt 84ab48c15c broadcom/vc4: Fix handling of GFXH-515 workaround with a start vertex count.
We failed to take the start into account for how many vertices to draw in
this round, so we would end up decrementing count below 0, which as an
unsigned number meant we would loop until the CLs soon ran out of space.

When I wrote the code I was thinking about how to use the previously
emitted shader state (no index bias baked into the elements) by emitting
up to 65535 and then only re-emitting with bias for the second wround, but
that doesn't work if the start is over 65535.  Instead, just delay
emitting shader state until we get into the drawarrays GFXH-515 loop and
always bake the bias in when we're doing the workaround.
2017-12-01 15:37:28 -08:00
Eric Anholt bcb6ebe91a broadcom/vc4: Fix the scaling factor for the GFXH-515 workaround.
For triangle strips, we step by max_verts - 2.
2017-12-01 15:37:28 -08:00
Dylan Baker f56e964e01 meson: use dep_thread instead of dependency('threads') in freedreno
They are the same thing, but this is more consistent with the rest of
the project.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-12-01 15:31:43 -08:00
Dylan Baker 5e71efef44 meson: Add lmsensors support
v2: - Make -Dlmsensors=false work
    - Simplify auto and true cases

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-12-01 15:31:43 -08:00
Eric Engestrom 29ee934331 gallium/hud: use #ifdef to test for macro existence
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-12-01 13:49:42 +00:00
Eric Engestrom 13a7a2d455 amd: remove always-true BRAHMA_BUILD define
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-01 13:49:42 +00:00
George Kyriazis 95adbe1a4e swr/scons: Fix intermittent build failure
gen_rasterizer*.cpp depends on gen_ar_eventhandler.hpp.
Account for new dependency.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2017-12-01 07:47:13 -06:00
Dave Airlie 4e7f6437b5 r600: add ARB_shader_storage_buffer_object support (v3)
This just builds on the image support. Evergreen only has ssbo
for fragment and compute no other stages.

v2: handle images and ssbo in the same shader properly (Ilia)
v3: fix RESQ on buffers,
    fix missing atom emit
    fix first element offset
    use R32 format
    write separate buffer rat store path.
(from running deqp gles3.1 tests)

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-01 06:12:31 +00:00
Dave Airlie c758fd05d8 r600/cayman: looks like cmpxchg moved to Z
On cayman it appears the cmp component is now in Z.

Fixes:
arb_shader_image_load_store-dead-fragments on cayman.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-01 03:59:17 +00:00
Dave Airlie 4f3e73516c r600/shader: fix 64->32 conversions
These didn't handle the TGSI at all properly, this fixes
them to use the common path for 64->32 then adds the 32->int
on at the end.

Fixes:
generated_tests/spec/arb_gpu_shader_fp64/execution/conversion/*

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-01 03:48:35 +00:00
Marek Olšák ed4780383c radeonsi/gfx9: fix importing shared textures with DCC
VI has 11 dwords at least. GFX9 has 10 dwords.

Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-30 18:46:11 +01:00
Tapani Pälli faccbaf3fa mesa: add AllowGLSLCrossStageInterpolationMismatch workaround
This fixes issues seen with certain versions of Unreal Engine 4 editor
and games built with that using GLSL 4.30.

v2: add driinfo_gallium change (Emil Velikov)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97852
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103801
Acked-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-30 11:43:10 +02:00
Wladimir J. van der Laan f1a9a724f9 etnaviv: GC7000: Factor out state based texture functionality
Prepare for two texture handling paths, the descriptor-based
path will be added in a future commit. These are structured
so that the texture implementation handles its own state
emission.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:33:20 +01:00
Wladimir J. van der Laan 075f8cd7de etnaviv: GC7000: Move active_samplers_bits to texture
This needs to be shared between texture_plain and texture_desc.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:33:16 +01:00
Wladimir J. van der Laan 260a5e2a1a etnaviv: GC7000: Factor out incompatible texture handling logic
This will be shared with the texture descriptor path.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:33:11 +01:00
Wladimir J. van der Laan 9d1f8805b0 etnaviv: GC7000: Track dirty sampler views
Need this to efficiently emit texture descriptor invalidations.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:33:07 +01:00
Wladimir J. van der Laan 5cc36f9f21 etnaviv: GC7000: Make point sprites work on HALTI5
Track varying component offset of the point size output, as well as
provide the offset of the point coord input.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:33:02 +01:00
Wladimir J. van der Laan 3d09bb390a etnaviv: GC7000: State changes for HALTI3..5
Update state objects to add new state, and emit function to emit new
state.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:32:33 +01:00