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freedreno/ir3: all mem instructions have WAR hazzard 

It isn't just load instructions that have write-after-read hazzard.

Fixes stk gaussian blur compute shaders.

Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark 2017-12-03 11:48:56 -05:00
parent e6c6495d3a
commit 48eef0c182
1 changed files with 1 additions and 1 deletions
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2
src/gallium/drivers/freedreno/ir3/ir3_legalize.c
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@ -211,7 +211,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
/* both tex/sfu appear to not always immediately consume
* their src register(s):
*/
if (is_tex(n) || is_sfu(n) || is_load(n)) {
if (is_tex(n) || is_sfu(n) || is_mem(n)) {
foreach_src(reg, n) {
if (reg_gpr(reg))
regmask_set(&needs_ss_war, reg);