Commit Graph

124001 Commits

Author SHA1 Message Date
Lionel Landwerlin 805b32cab9 intel: add identifier for debug purposes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin e81de67d85 i965: store workaround_bo offset
This offset store the location where we read/write into the
workaround_bo. It will allow to select a different address later,
leaving the beginning of the buffer to some other use.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin 07781f0afe iris: store workaround address
This will allow to select a different address later, leaving the
beginning of the buffer to some other use.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin 33b452aae7 anv: store the workaround address
This will allow to select a different address later, leaving the
beginning of the buffer to some other use.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin 0ff5b9e692 blorp: rename workaround address function
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin f36708b143 anv: fixup unwinding of device create failure
We appear to have the ordering mixed up a bit.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Icecream95 faf28b83fd panfrost: Enable PIPE_CAP_VERTEX_COLOR_UNCLAMPED
This tells Mesa to clamp vertex colours in the vertex shader.

This improves rendering in a number of games such as Extreme Tux
Racer and H-Craft Championships.

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5075>
2020-05-20 15:14:28 +00:00
Andrii Simiklit 3725aa7b5d glsl_type: don't serialize padding bytes from glsl_struct_field
This should fix such valgrind warnings:
==37417== Uninitialised byte(s) found during client check request
==37417==    at 0x6183471: blob_write_bytes (blob.c:163)
==37417==    by 0x629785B: encode_type_to_blob (glsl_types.cpp:2760)
==37417==    by 0x61E68D8: write_variable (nir_serialize.c:293)
==37417==    by 0x61E6F6A: write_var_list (nir_serialize.c:421)
==37417==    by 0x61EBA7A: nir_serialize (nir_serialize.c:2018)
==37417==    by 0x5B5E007: serialize_nir_part (brw_program_binary.c:135)
==37417==    by 0x5B5E7F3: brw_serialize_program_binary (brw_program_binary.c:299)
==37417==    by 0x5FEF5FF: write_program_payload (program_binary.c:177)
==37417==    by 0x5FEF7BB: _mesa_get_program_binary_length (program_binary.c:225)
==37417==    by 0x5E3D31D: get_programiv (shaderapi.c:912)
==37417==    by 0x5E3F730: _mesa_GetProgramiv (shaderapi.c:1827)
==37417==    by 0x111DA0: program_binary_save_restore (shader_runner.c:686)
==37417==  Address 0x8f59481 is 81 bytes inside a block of size 480 alloc'd
==37417==    at 0x483B7F3: malloc (vg_replace_malloc.c:309)
==37417==    by 0x618CE67: ralloc_size (ralloc.c:123)
==37417==    by 0x618CF35: rzalloc_size (ralloc.c:155)
==37417==    by 0x618D245: rzalloc_array_size (ralloc.c:234)
==37417==    by 0x629041D: glsl_type::glsl_type(glsl_struct_field const*, unsigned int, glsl_interface_packing, bool, char const*) (glsl_types.cpp:148)
==37417==    by 0x6293EC3: glsl_type::get_interface_instance(glsl_struct_field const*, unsigned int, glsl_interface_packing, bool, char const*) (glsl_types.cpp:1271)
==37417==    by 0x604C878: (anonymous namespace)::per_vertex_accumulator::construct_interface_instance() const (builtin_variables.cpp:365)
==37417==    by 0x6050722: (anonymous namespace)::builtin_variable_generator::generate_varyings() (builtin_variables.cpp:1568)
==37417==    by 0x60509CA: _mesa_glsl_initialize_variables(exec_list*, _mesa_glsl_parse_state*) (builtin_variables.cpp:1600)
==37417==    by 0x6149AE9: _mesa_ast_to_hir(exec_list*, _mesa_glsl_parse_state*) (ast_to_hir.cpp:131)
==37417==    by 0x60706D6: _mesa_glsl_compile_shader (glsl_parser_extras.cpp:2222)
==37417==    by 0x5E3DC16: _mesa_compile_shader (shaderapi.c:1211)

==37417== Use of uninitialised value of size 8
==37417==    at 0x529AE13: ??? (in /usr/lib/x86_64-linux-gnu/libz.so.1.2.11)
==37417==    by 0x6184075: util_hash_crc32 (crc32.c:127)
==37417==    by 0x5FEF401: write_program_binary (program_binary.c:95)
==37417==    by 0x5FEF8BC: _mesa_get_program_binary (program_binary.c:252)
==37417==    by 0x5E40E22: _mesa_GetProgramBinary (shaderapi.c:2411)
==37417==    by 0x4914057: stub_glGetProgramBinary (piglit-dispatch-gen.c:24737)
==37417==    by 0x111E4A: program_binary_save_restore (shader_runner.c:704)
==37417==    by 0x11F765: piglit_display (shader_runner.c:5112)
==37417==    by 0x499082F: run_test (piglit_fbo_framework.c:52)
==37417==    by 0x4980E89: piglit_gl_test_run (piglit-framework-gl.c:229)
==37417==    by 0x110DA9: main (shader_runner.c:72)

v2: - decode_glsl_struct_field_from_blob and
    encode_glsl_struct_field should be `static`
    ( Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> )
v3: - we can get rid of `struct packed_struct_field_flags`
    ( Tapani Pälli <tapani.palli@intel.com> )
    - we can get rid of `unsigned __pad: 15` bitfield
    ( Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> )

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Andrii Simiklit <asimiklit.work@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5054>
2020-05-20 14:15:00 +00:00
Jonathan Marek 0d9996e223 turnip: enable 422_UNORM formats
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4590>
2020-05-20 13:22:12 +00:00
Jonathan Marek d070a7ba0c turnip: implement VK_KHR_sampler_ycbcr_conversion
Most changes based on radv, some simplification, since we don't need to
sample multiple planes, 422_UNORM/420_UNORM formats will be supported
directly using the hardware formats for those.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4590>
2020-05-20 13:22:12 +00:00
Jonathan Marek 70502f071c freedreno/registers: document 422_UNORM and 420_UNORM formats
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4590>
2020-05-20 13:22:12 +00:00
Jonathan Marek 75d7ee8029 util/format: translate 422_UNORM and 420_UNORM vulkan formats
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4590>
2020-05-20 13:22:12 +00:00
Lionel Landwerlin d0e11231a4 intel/perf: repurpose INTEL_DEBUG=no-oaconfig
We initially used this debug option to mean "don't bother registering
the OA configuration into the kernel".

This change makes this option suppress any interaction with the
i915/perf interface. This is useful when debugging self modifying
batches with performance queries while running on the intel_mi_runner.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin 2001a80d4a anv: Implement VK_KHR_performance_query
This has the same kernel requirements are VK_INTEL_performance_query

v2: Fix empty queue submit (Lionel)

v3: Fix autotool build issue (Piotr Byszewski)

v4: Fix Reset & Begin/End in same command buffer, using soft-pin &
    relocation on the same buffer won't work currently. This version
    uses a somewhat dirty trick in anv_execbuf_add_bo (Piotr Byszewski)

v5: Fix enumeration with null pointers for either pCounters or
    pCounterDescriptions (Piotr)
    Fix return condition on enumeration (Lionel)
    Set counter uuid using sha1 hashes (Lionel)

v6: Fix counters scope, should be COMMAND_KHR not COMMAND_BUFFER_KHR (Lionel)

v7: Rebase (Lionel)

v8: Rework checking for loaded queries (Lionel)

v9: Use new i915-perf interface

v10: Use anv_multialloc (Jason)

v11: Implement perf query passes using self modifying batches (Lionel)
     Limit support to softpin/gen8

v12: Remove spurious changes (Jason)

v13: Drop relocs (Jason)

v14: Avoid overwritting .sType in
     VkPerformanceCounterKHR/VkPerformanceCounterDescriptionKHR (Lionel)

v15: Don't copy the entire
     VkPerformanceCounterKHR/VkPerformanceCounterDescriptionKHR (Jason)
     Reuse anv_batch rather than custom packing (Jason)

v16: Fix missing MI_BB_END in reconfiguration batch
     Only report the extension with kernel support (perf_version >= 3)

v17: Some cleanup of unused stuff

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin ceb822f9e0 intel/perf: reuse offset specified in the query
The current code relies on the order of the function
gen_perf_query_result_accumulate() to match the descriptions written
by gen_perf.py. Let's just reuse the offset specified in the python
script.

v2: Use accumlator offsets more (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin 63c193e921 anv: use a query filled by the perf code
We're about to use the offset fields from the query object. We can't
just use a made up object.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin 93924ab091 intel/perf: report whether the platform supported
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin fe8e8e5099 intel/perf: add counter category to generated code
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin c36933e081 intel/perf: add helper to compute metrics from counters
The produced array tells use what metric to enable for a given pass.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin a7890f559b intel/perf: emit counter units in generated code
We'll use this coming extension.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin d15369332f intel/perf: compute number of passes for a set of counters
We want to compute the number of passes required to gather performance
data about a set of counters.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin 3f0c4c2afe intel/perf: create a unique list of counters
For a future extension we want to be able to list the counters. Our
existing sets counters might contain the same counters multiple times.
This is a side effect of the fixed OA counters in the HW. We track
thoses with a mask so that we know when a counter is available from
multiple metrics.

v2: Use BITFIELD64_BIT() (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin 65d242ff5e intel/perf: update generated code to ralloc all data
Previously counter descriptions as well register values were written
in global static variables. This isn't really thread safe so instead
ralloc all the data back under the gen_perf_config object.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin a683e7f3dc intel/perf: store the appropriate OA formats in queries
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin 8b8eaa84a3 intel/perf: make pipeline statistic query loading optional
On Vulkan most of those are already covered by standard queries so
add the ability to skip them.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin cc13bfbd05 intel/genxml: add PIPE_CONTROL command cache invalidate bit
This new bit invalidates the cache/prefetch of commands in the command
streamer. This will be useful for self modifying batches.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin 34a0ce58c7 anv: add a new execution mode for secondary command buffers
This change adds a call/return execution mode for secondary command
buffer rather than the existing copy into the primary batch mode.

v2: Rework convention to avoid burning an ALU register (Jason)

v3: Use anv_address_add() (Jason)

v4: Move command emissions to anv_batch_chain.c (Jason)

v5: Also move last MI_BBS emission in secondary command buffer to
    anv_batch_chain.c (Jason)

v6: Fix end secondary command buffer end (Jason)

v7: Refactor anv_batch_address() to remove additional emit functions

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin a96d92a689 anv: don't reserve a particular register for draw count
By using the same mi_builder throughout the draw call, we can just
allocate a register from the mi_builder and unref it when we're done.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin 796fccce63 intel/mi-builder: add framework for self modifying batches
v2: Use Jason's idea to store addresses to modify

v3: Add ALU flushes (Jason)

v4: Remove ALU flush from gen_mi_self_mod_barrier() (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin 570bd760d3 intel/genxml: fix bits generation for MI_LOAD_REGISTER_IMM
This instruction has a group with the same name than another field above :

  <field name="Data DWord" start="64" end="95" type="uint"/>
  <group count="0" start="96" size="64">
    <field name="Register Offset" start="2" end="22" type="offset"/>
    <field name="Data DWord" start="32" end="63" type="uint"/>
  </group>

The script was replacing the offset of the field first with the second
one in the group.

This change ignore anything a group within an instruction.

v2: Drop unused variable (Rafael)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:26 +03:00
Denys ee9b17fc26 gitlab: Ask about reproduction rate in the issue template
Reviewed-by: <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5055>
2020-05-20 10:20:00 +00:00
Jason Ekstrand 989619c05b nir: Add const to nir_intrinsic_src_components
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5108>
2020-05-19 20:45:55 +00:00
Alyssa Rosenzweig 29afa88941 pan/mdg: Apply outmods
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:28 +00:00
Alyssa Rosenzweig db7b0eb911 pan/mdg: Use helpers for branch/discard inversion
Doesn't come up on glmark but would covered by the old passes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:28 +00:00
Alyssa Rosenzweig 5500b1f280 pan/mdg: Remove invert optimizations
Unused since last commit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:28 +00:00
Alyssa Rosenzweig 449e5ded93 pan/mdg: Treat inot as a modifier
With this, we may remove all invert passes and simply look at the src
modifier on NIR->MIR and fixup at pack time. No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:28 +00:00
Alyssa Rosenzweig b124f5315c pan/mdg: Apply abs/neg modifiers
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig 24e2e24dc0 pan/mdg: Ingest fsat_signed/fclamp_pos
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig 22bb5a9acb pan/mdg: Prepare for modifier helpers
We have to restructure to ensure NIR->MIR does not mutate the NIR and to
allow passing around dest/outmods for the new helpers. If NIR->MIR were
better designed this would be easier. Sigh.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig f0455de6fc pan/mdg: Drop nir_lower_to_source_mods
shader-db regressions fixed shortly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig acc5afb0af pan/mdg: Remove .pos propagation pass
Will be replaced later in the series. shader-db regressions but those
fixed momentarily.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig aeb55180ff panfrost: Add modifier detection helpers
With the goal of removing modifiers from NIR, these helpers let us
detect modifier patterns without mutating the underlying NIR. These were
intended for upstream, but due to various issues are being (temporarily)
vendored.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig c2b0f3c17d nir: Add fclamp_pos opcode
Corresponds to the .pos modifier on all Mali GPUs (lima and panfrost).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig 0aedce417a nir: Add fsat_signed opcode
Exists on later Mali. Equivalent to clamp(x, -1.0, 1.0)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
2020-05-19 20:21:27 +00:00
Connor Abbott 518909290b tu: Support VK_FORMAT_FEATURE_BLIT_SRC_BIT for texture-only formats
It turns out this is required for compressed formats, and we might as
well enable it for the one other texture-only format too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
2020-05-19 19:55:11 +00:00
Connor Abbott 74f1c304e8 tu: Fix buffer compressed pitch calculation with unaligned sizes
We can just set the extent and not bufferRowLength/bufferImageHeight,
and the extent may not be a multiple of the block size if it covers the
entire image. In this case we have to first divide to get the
width/height in terms of blocks, and then multiply by the block size to
get the buffer's pitch and layer size. Multiplying and dividing instead
won't get the correct result when the extent covers the entire image and
isn't a multiple of the block size. This also makes the code easier to
follow because we don't calculate a pitch in non-sensical units (bytes
times the block width) as an intermediate step.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
2020-05-19 19:55:11 +00:00
Connor Abbott da68c72715 tu: Fall back to 3d blit path for BC1_RGB_* formats
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
2020-05-19 19:55:11 +00:00
Connor Abbott 3d5cc5ff22 tu: Always initialize image_view fields for blit sources
Previously we only supported BLIT_SRC_BIT and BLIT_DEST_BIT together, so
we didn't have to worry about initializing blit-related fields for
texture-only formats, but it turns out that 2d blits work out just fine
with these formats and we'll need to enable BLIT_SRC_BIT for
texture-only formats due to a Vulkan requirement on compressed formats.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
2020-05-19 19:55:11 +00:00
Jason Ekstrand cc4a02d0ed nir: Add a store_reg helper and use the builder in phis_to_regs
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5094>
2020-05-19 19:31:26 +00:00
Jason Ekstrand 3fdbeb70e1 nir: Add a new helper for iterating phi sources leaving a block
This takes the same callback as nir_foreach_src except it walks all phi
sources which leave a given block.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5094>
2020-05-19 19:31:26 +00:00