Commit Graph

95875 Commits

Author SHA1 Message Date
Dave Airlie 76ac8fafad radv/winsys: use amdgpu_bo_va_op_raw.
This is a precursor to the gfx9 fix to use uncached for the event
memory. Move to the interface which allows setting the flags,
but wrap it to avoid having to copy it around the place.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07 21:04:24 +01:00
Leo Liu 6e8ef53837 Revert "st/va: add enviromental variable to disable interlace"
This reverts commit 10dec2de2d.

The environment variable is no longer needed with the previous change

Reviewed-by: Christian König <christian.koenig@amd.com>
2017-09-07 13:32:36 -04:00
Leo Liu 15d4d44d9b st/va: move YUV content to deinterlaced buffer when reallocated for encoder
v2: use deinterlace common function
v3: make sure deinterlace only

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-09-07 13:32:36 -04:00
Leo Liu cadeb73f6b st/va: reallocate the buffer if the layout isn't supported
So that it makes more clear for buffer reallocation based
on buffers layout for both decoder and encoder.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-09-07 13:32:36 -04:00
Leo Liu 78ec7400c5 vl/compositor: make vl_compositor_set_yuv_layer() static
Since it's no longer being called outside of compositor

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-09-07 13:32:36 -04:00
Leo Liu 9f32078c20 st/omx: use vl/compositor helper function for YUV deinterlacing
v2: separate helper function in different patch

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-09-07 13:32:36 -04:00
Leo Liu a6da7e6c3a vl/compositor: make a helper function for YUV deinterlacing
The similar function is in OMX, and only used by OMX. Now have it
moved to vl/compositor for other state tracker to use later.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-09-07 13:32:36 -04:00
Marek Olšák 4bd2bdbb3c ac/surface: add radeon_surf::has_stencil for convenience
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 17:59:37 +02:00
Gert Wollny c4741bbb6f mesa/st/tests: Fix regressions with libunwind enabled introduced with 7be6d8fe12
Add the according flags to link with libunwind.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=102565
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 14:14:02 +02:00
Gert Wollny ab16538b83 mesa/st/tests: Fix classic build regressions introduced with 7be6d8fe12
Fixes the build in classic only mode, i.e. the new state tracker tests are
only build when Gallium is enabled.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 14:13:43 +02:00
Iago Toral Quiroga 580fc06c61 mesa/main: Fix GetTransformFeedbacki64 for glTransformFeedbackBufferBase
The spec has special rules for querying buffer offsets and sizes
when BindBufferBase is used, described  in the OpenGL 4.6 spec,
section 6.8 Buffer Object State:

   "To query the starting offset or size of the range of a buffer
    object binding in an indexed array, call GetInteger64i_v with
    target set to respectively the starting offset or binding size
    name from table 6.5 for that array. Index must be in the range
    zero to the number of bind points supported minus one. If the
    starting offset or size was not specified when the buffer object
    was bound (e.g. if it was bound with BindBufferBase), or if no
    buffer object is bound to the target array at index, zero is
    returned."

Transform feedback buffer queries should follow the same rules, since
it is the same case for them. There is a CTS test for this.

Fixes:
KHR-GL45.direct_state_access.xfb_buffers

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2017-09-07 14:01:15 +02:00
Marek Olšák 7ec64bd88c radeonsi: don't read tcs_out_lds_layout.patch_stride from an SGPR
Same as before, writing TCS outputs to LDS is rare.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 13:00:07 +02:00
Marek Olšák 07fe10c75d radeonsi: don't read tcs_out_lds_layout.vertex_size from an SGPR
TCS outputs are usually not written to LDS, so no stats here.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 13:00:07 +02:00
Marek Olšák 89bf8668c2 radeonsi/gfx9: don't read LS out vertex stride from an SGPR in monolithic HS
-44 bytes in a monolithic LS-HS binary.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 13:00:07 +02:00
Marek Olšák f974bb768b radeonsi: don't read the LS output vertex stride from an SGPR in LS
Now it's able to generate ds_write2_b64 instead of ds_write2_b32.

-20 bytes in one shader binary. (having only 1 output)

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 13:00:07 +02:00
Marek Olšák 22f5dfd300 radeonsi: don't read the number of TCS out vertices from an SGPR in TCS
-16 bytes in one shader binary.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 13:00:07 +02:00
Marek Olšák 17dd4856a6 radeonsi: don't always apply the PrimID instancing bug workaround on SI
It looks like commit 391673af7a that should
have fixed the perf regression didn't really change much if anything.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 13:00:06 +02:00
Marek Olšák a0823df148 radeonsi: remove 2 callbacks from si_shader_context
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 13:00:06 +02:00
Marek Olšák 1cda9a2fee winsys/amdgpu: disable local BOs on Raven
It hangs with a high degree of reproducibility.

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 12:57:48 +02:00
Marek Olšák 7b4b8f6373 disk_cache: make the thread queue resizable and low priority
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 12:57:14 +02:00
Thomas Hellstrom e96d175c7d loader/dri3: Make sure we invalidate a drawable on size change
If we're seeing a drawable size change, in particular after processing a
configure notify event, make sure we invalidate so that the state tracker
picks up the new geometry.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-09-07 12:43:29 +02:00
Thomas Hellstrom a727c804a2 loader/dri3: Process event after each fence wait
This tries to mimic dri2 behaviour where events are typically processed
while waiting for X replies. Since, during steady-state dri3 rendering, we
seldom wait for xcb replies, and haven't enabled any automatic event
processing, instead check for events after a fence wait.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-09-07 12:43:29 +02:00
Marek Olšák e4018fdd85 st/mesa: skip draw calls with pipe_draw_info::count == 0
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102502

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Tested-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-07 12:34:28 +02:00
Eric Engestrom 6c2e0527ea docs: update envvar docs to reflect MESA_NO_ERROR change
I changed the behaviour earlier today, but forgot to update the
corresponding docs.

Fixes: 77713a0acb "mesa: allow user to set MESA_NO_ERROR=0"
Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-07 11:16:31 +01:00
Samuel Pitoiset 86b99893eb radv: do not use a bitfield when dirtying the vertex buffers
Useless to track which one has been updated because we
re-upload all the vertex buffers in one shot.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-09-07 10:01:21 +02:00
Samuel Pitoiset 2408f616e8 radv: remove unused radv_meta_saved_state::vertex_saved field
It's always false.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-09-07 10:01:21 +02:00
Eric Engestrom 77713a0acb mesa: allow user to set MESA_NO_ERROR=0
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102530
Cc: Michel Dänzer <michel@daenzer.net>
Cc: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-09-07 08:54:44 +01:00
Eric Engestrom 56f16c4fbb util: rename include guard to avoid clash
src/mesa/main/debug.h uses the same include guard.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 08:54:44 +01:00
Roland Scheidegger 6d9d6071ee llvmpipe, tgsi: hook up dx10 gather4 opcode
Trivial. We already support tg4 for legacy tex opcodes, so the actual
texture sampling code already handles it.
(Just like TG4, we don't handle additional capabilities and always sample
red channel.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-09-07 03:32:01 +02:00
Roland Scheidegger de6810d9be llvmpipe, draw: increase shader cache limits
We're not particularly concerned with memory usage, if the tradeoff is
shader recompiles. And it's common for apps to have a lot of shaders
nowadays (and, since our shaders include a LOT of context state of course
we may create quite a bit more shaders even).
So quadruple the amount of shaders draw will cache (from 128 to 512).
For llvmpipe (fs shaders) quadruple the number of instructions, keep the
number of variants the same for now (only with very simple, non-texturing
shaders the variant limit could really be reached), and simplify the
definition, it's probably easier to just have one different definition
per branch...

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-09-07 03:32:01 +02:00
Dave Airlie e852ecd22b ac/surface: reduce gfx9_surface_layout size.
152->144.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07 11:00:08 +10:00
Dave Airlie cc73ab9884 radv: reduce radv_amdgpu_winsys struct size.
1168->1160.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07 11:00:08 +10:00
Dave Airlie 3cc620bf55 radv: reduce radv_image struct size.
1480->1472.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07 11:00:08 +10:00
Dave Airlie 66031d8925 radv: reduce radv_shader_variant struct size.
544->536

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07 11:00:08 +10:00
Dave Airlie a2c2a76c9e radv: reduce radv_cmd_state struct size.
1632->1624.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07 11:00:08 +10:00
Dave Airlie f45e768413 radv: reduce meta_saved_state struct size.
904->896.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07 11:00:07 +10:00
Dave Airlie 42d50c779b nir: put compact into bitfields in nir_variable_data
This being declared bool means it won't get merged with the previous
bitfields, this seems like an oversight rather than deliberate.

Noticed when running pahole.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07 11:00:04 +10:00
Chad Versace ec8ed2f277 anv: Annotate entrypoint table with index and func name
This helps when debugging a broken entrypoint table.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-06 13:07:12 -07:00
Leo Liu e1e3c0384b radeon/uvd: fix the assertion check for YUYV format
Fixes:7319ff87("radeon/uvd: add YUYV format support for target buffer")

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-09-06 15:53:18 -04:00
Anuj Phogat ad160c2273 intel: Add brand string for KBL-R
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-09-06 10:09:44 -07:00
Anuj Phogat 4c4c28ca70 intel: Remove unused device info for KBL GT1.5
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-09-06 10:09:38 -07:00
Anuj Phogat 9c588ffdfb intel: Change a KBL pci id to GT2 from GT1.5
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-09-06 10:09:34 -07:00
Anuj Phogat a000fca415 intel: Fix few KBL brand strings
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-09-06 10:09:25 -07:00
Anuj Phogat ebc5ccf3cc intel: Remove unused Kabylake pci ids
These PCI IDs are not used in any Kabylake SKUs.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-09-06 10:08:58 -07:00
Emil Velikov d03b06b35e Revert "Android: add -Wno-date-time flag for clang"
This reverts commit 6dae9176d6.

No longer needed as of last commit.

Cc: Rob Herring <robh@kernel.org>
2017-09-06 17:48:51 +01:00
Emil Velikov 54a789aa2a mesa: replace date/time macros with MESA_GIT_SHA1
Former is non-deterministic, results in non-reproducible builds and
compilers throw a warning about it.

Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-06 17:48:50 +01:00
Emil Velikov acf7f84564 mesa: don't use %s for PACKAGE_VERSION macro
The macro itself is a well defined string, which cannot cause issues
with printf or other printf-like functions.

All other places through Mesa already use it directly, so let's update
the final two instances.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-06 17:48:50 +01:00
Emil Velikov d0a4b26915 docs/release-calendar: update and extend
v2: Correct 17.1.10 version, adjust some names.
v3: Add missing <tr> (Andres)

Cc: Juan A. Suárez <jasuarez@igalia.com>
Cc: Andres Gomez <agomez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
2017-09-06 17:48:50 +01:00
Emil Velikov cf6e6eb5cd docs/releasing: polish LLVM_CONFIG wording/handling
Use consistent way to manage "non-default" llvm installations, clearly
documenting it.

AKA, use LLVM_CONFIG throughout and unset for the Windows/mingw builds.

v2: unset the save_ variable (Andres)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
2017-09-06 17:48:50 +01:00
Emil Velikov 0f24660245 docs/releasing: remove -jX instances
One can control the number of jobs via MAKEFLAGS. As such there's
little reason to set the number of jobs for each make invocation.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-06 17:48:50 +01:00