Commit Graph

89099 Commits

Author SHA1 Message Date
Jason Ekstrand f8dfe9b826 intel/isl: Add format metadata for typed reads/writes
This adds two columns to the format table as well as two helpers for
determining whether or not a given format is supported for typed reads
and writes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-14 07:50:13 -08:00
Jason Ekstrand 0ef14cdc98 anv/cmd_buffer: Return a VkResult from verify_cmd_parser
This fixes a "statement with no effect" compiler warning

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-14 07:50:13 -08:00
Ilia Mirkin 956556b3c3 nvc0: disable linked tsc mode in compute launch descriptor
Empirically, this makes things work. Presumably this was originally
copied from the blob, which does make use of linked tsc mode.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99532
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2017-02-13 20:10:53 -05:00
Anuj Phogat 5e2909e732 mesa: Add EXT_frag_depth bits and enable it on all drivers
Passes the newly added piglit test for this extension on i965.

V2: Fix comments by Ilia.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-02-13 16:08:40 -08:00
Dave Airlie b3b4114a0f radeonsi: use common sendmsg emission function.
This just ports radeonsi to use the sendmsg common code.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-14 00:03:22 +00:00
Dave Airlie e3324e0c60 radv/ac: use sendmsg emission interface.
This uses the common code to emit the correct intrinsic.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-14 00:03:18 +00:00
Dave Airlie f32955be43 radeon/ac/llvm: add support for sendmsg emission
This lets us use the new intrinsic on the correct
version of llvm.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-14 00:02:50 +00:00
Dave Airlie f77d2871ac radv: disable gfx init on CIK for now
Luzipher on irc report this hangs his Hawaii, disable for now
until I get time to debug.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-14 08:01:39 +10:00
Dave Airlie 69fc7a2c82 tgsi: fix memory leak in tgsi sanity check
This just fixes this without repeating the code.

Reported-by: Li Qiang
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-14 08:00:30 +10:00
Dave Airlie 62fef3e159 radv/ac: use common interp code for new intrinsics
This uses the common fs interp code to use the new
llvm intrinsics so llvm can drop the old ones.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-14 07:48:01 +10:00
Dave Airlie 592069c1fb radv: use indirect buffer for initial gfx state.
This puts the common gfx state for the device into an
indirect buffer, and just calls out to it, on CIK and above.

This is taken from what radeonsi does.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-13 20:02:45 +00:00
Dave Airlie b26253b34d radv: start splitting init config up
This is just prep work for the following patch to use
a common gfx init indirect buffer.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-13 20:02:34 +00:00
Dave Airlie 604e562e5b radv: don't pass physical device to si_init_ fns.
This is just a trivial cleanup.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-13 20:02:06 +00:00
Dave Airlie 8b47b97215 radv: detect command buffers that do no work and drop them (v2)
If a buffer is just full of flushes we flush things on command
buffer submission, so don't bother submitting these.

This will reduce some CPU overhead on dota2, which submits a fair
few command streams that don't end up drawing anything.

v2: reorganise loop to count first then malloc,
rename some vars (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-13 20:00:28 +00:00
Jason Ekstrand d49d275c41 anv/blorp: Don't sanitize the swizzle for blorp_clear
BLORP is now smart enough to handle any swizzle (even those that contain
ZERO or ONE) in a reasonable manner.  Just let BLORP handle it.  This
fixes the following Vulkan CTS tests on Haswell:

 - dEQP-VK.api.image_clearing.clear_color_image.1d_b4g4r4a4_unorm_pack16
 - dEQP-VK.api.image_clearing.clear_color_image.2d_b4g4r4a4_unorm_pack16
 - dEQP-VK.api.image_clearing.clear_color_image.3d_b4g4r4a4_unorm_pack16

Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-02-13 09:24:49 -08:00
Jason Ekstrand e233db6e93 intel/blorp: Swizzle clear colors on the CPU
It's trivial to swizzle clear colors on the CPU, easily deals with the
hardware restrictions for render target swizzles, and makes swizzled
clears work on all hardware as opposed to just HSW+.

Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-02-13 09:24:43 -08:00
Emil Velikov bd1c61261f docs: add news item and link release notes for 17.0.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-02-13 12:05:34 +00:00
Emil Velikov 437b6a136e docs: add sha256 checksums for 17.0.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 80b41d9899f37e58b197f55897115d2cb6e13af9)
2017-02-13 12:02:58 +00:00
Emil Velikov 2343b8a262 docs: Update 17.0.0 release notes
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 683462e680326ee0cd7a794f018178b7b5573c4f)
2017-02-13 12:02:56 +00:00
Emil Velikov 20ccff56a0 st/xlib: remove always true ifdef GLX_EXTENSION guards
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
2017-02-13 10:15:02 +00:00
Emil Velikov 884fd1262f xlib: remove always true ifdef GLX_EXTENSION guards
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
2017-02-13 10:14:40 +00:00
Emil Velikov 261d5e4c6d glx: remove always true XDAMAGE_1_1_INTERFACE guard
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-02-13 10:14:32 +00:00
Emil Velikov 87f485e957 scons: check for libXdamage 1.1 or later
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-02-13 10:14:23 +00:00
Emil Velikov 43b09ee0b2 configure.ac: check for libXdamage 1.1 or later
Released back in 2007 so it should not be an issue for anyone building
from git.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-02-13 10:14:06 +00:00
Emil Velikov bfac8d1749 glx: remove DRI2DriverPrimeShift compile guards
DRI2DriverPrimeShift was added in dri2proto-2.8, which we now require
as of the previous commit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-02-13 10:13:46 +00:00
Emil Velikov a1662d0dab vl: remove DRI2DriverPrimeShift compile guards
DRI2DriverPrimeShift was added in dri2proto-2.8, which we now require as
of the previous commit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-02-13 10:13:29 +00:00
Emil Velikov cd1ebd8aba scons: add missing dri2proto requirement
Noticed while skimming through, although admittedly there's many other
dependencies that are not tracked by the scons build.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-02-13 10:13:24 +00:00
Emil Velikov 6689cc0392 configure.ac: dump dri2proto requirement to 2.8
dri2proto 2.8 was released 4+ years ago, so it must be of no surprise
for anyone building mesa from git.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-02-13 10:12:56 +00:00
Emil Velikov 404a5ca088 glx: remove always true ifdef guards
The two symbols referenced were introduced with v2.2 and 2.3 of
the dri2proto package and we require dri2proto >= 2.6.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-02-13 10:12:36 +00:00
Emil Velikov 4f080b46a8 winsys/intel: remove unused winsys - ilo was its only user
Cc: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-02-13 10:09:52 +00:00
Emil Velikov 6ffddba33b configure.ac: do not use deprecated macros - AC_HELP_STRING AC_ERROR
Replace with AS_HELP_STRING and AC_MSG_ERROR respectively, as spotted by
autoupdate.

Note that the suggested AC_CANONICAL_SYSTEM > AC_CANONICAL_TARGET change
is not addressed here since that requires very extensive testing.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-02-13 10:09:45 +00:00
Timothy Arceri 0cbde643eb util/disk_cache: correctly use stat(3)
I forgot to error check stat() and also I wasn't using the subdir in
is_two_character_sub_directory().

Fixes: d7b3707c61 "util/disk_cache: use stat() to check if entry is a directory"
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-02-13 10:01:12 +00:00
Michel Dänzer 0f53404565 configure.ac: Drop LLVM compiler flags more radically
Drop all -m*, -W*, -O*, -g* and -f* flags, with the exception of
-fno-rtti, which must be used if it's part of the llvm-config --cxxflags
output. We don't want LLVM to dictate the flags we use, and it can even
cause build failures, e.g. if LLVM and Mesa are built with different
compilers.

While we're at it, eat any whitespace preceding dropped flags as well.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-02-13 16:07:37 +09:00
Kenneth Graunke 57dc6d80a0 glsl: Drop resize-to-MaxPatchVertices hack.
TCS and TES inputs without an array size are implicitly sized to
gl_MaxPatchVertices.  But TCS outputs are apparently not:

   "If no size is specified, it will be taken from the output patch size
    (gl_VerticesOut) declared in the shader."

Fixes dEQP-GLES31.functional.program_interface_query.program_output.
array_size.separable_tess_ctrl.var.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2017-02-12 21:09:25 -08:00
Kenneth Graunke 1fad070f96 mesa: Ignore per-vertex array size in SSO pipeline validation.
We were already unwrapping types when the producer was a non-array
stage and the consumer was an arrayed-stage...but we ought to unwrap
both ends for TCS -> TES matching too.

This will allow us to drop the "resize to gl_MaxPatchVertices" check
shortly, which breaks some things.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2017-02-12 21:09:23 -08:00
Kenneth Graunke e99df398f1 glsl: Update a comment about link errors for TCS && !TES.
OpenGL ES actually has spec text to prohibit this.  It's just OpenGL
that's confusing.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2017-02-12 21:09:21 -08:00
Kenneth Graunke 365afbdaef mesa: Do a draw time check for TES && !TCS in ES 3.x.
ES 3.x requires both TCS and TES to be present.  We already checked
the TCS && !TES case above, so we just have to check !TCS && TES here.

Note that this is allowed in OpenGL, just not ES.

This fixes a subcase of:
dEQP-GLES31.functional.debug.negative_coverage.*.tessellation.single_tessellation_stage

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2017-02-12 21:09:19 -08:00
Kenneth Graunke 05a56893aa mesa: Do (TCS && !TES) draw time validation in ES as well.
Now that we have OES_tessellation_shader, the same situation can occur
in ES too, not just GL core profile.

Having a TCS but no TES may confuse drivers - i965 crashes, for example.

This prevents regressions in
ES31-CTS.core.tessellation_shader.single.xfb_captures_data_from_correct_stage
with some SSO pipeline validation changes I'm making.

v2: Add an ES spec citation (suggested by Alejandro)

Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2017-02-12 21:09:14 -08:00
Jason Ekstrand c59d1ea51b i965/sampler_state: Set the "Base Mip Level" field on Sandy Bridge
Fixes two GL ES 3.0 CTS tests on Sandy Bridge:

ES3-CTS.functional.texture.mipmap.cube.base_level.linear_linear
ES3-CTS.functional.texture.mipmap.cube.base_level.linear_nearest

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
2017-02-12 17:56:32 -08:00
Jason Ekstrand c4f8f395b2 i965/sampler_state: Pass texObj into update_sampler_state
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
2017-02-12 17:56:32 -08:00
Jason Ekstrand 9df3778016 i965/sampler_state: Clamp min/max LOD to 14 on gen7+
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-02-12 17:56:32 -08:00
Ilia Mirkin 3970257cef st/mesa: don't pass compare mode for stencil-sampled textures
Fixes dEQP-GLES31.functional.stencil_texturing.misc.compare_mode_effect

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2017-02-12 19:26:25 -05:00
Ilia Mirkin 3f8b886e73 nv50,nvc0: use alternate samplers for stencil
The blob uses these, and it fixes a bunch of dEQP stencil sampling tests
involving border colors. Probably the Z-based samplers work somehow
differently wrt border colors when using the stencil swizzle.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-02-12 18:22:17 -05:00
Bas Nieuwenhuizen 1811ccf125 radv: Fix radv_GetPhysicalDeviceQueueFamilyProperties2KHR.
The struct have different size, so the arrays have different stride.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-02-13 00:18:19 +01:00
Wladimir J. van der Laan 55e00c7cfe etnaviv: Set shader instruction area correctly for GC3000
- Use the same instruction area on GC3000 as the Vivante driver.
  This allows the same number of instructions on GC3000 as GC2000
  instead of half.

- Makes sure that the "PE to FE" stall before updating the shader code
  or constants is hit (which is conditional on vs_offset > 0x4000). This
  is necessary on GC3000 too, it increases stability.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-02-12 20:42:37 +01:00
Wladimir J. van der Laan 0fe60e4fcc etnaviv: Update hw header files
Update from etnaviv repository rnndb. This adds some newly
discovered state for GC3000 (and some GC2000) features.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-02-12 20:38:56 +01:00
Dave Airlie f466d4dd6a radv: reduce CPU overhead merging bo lists.
Just noticed we do a fair bit of unneeded searching here.

Since we know that the buffers in a CS are unique already,
the first time we get any buffers, we can just memcpy those into
place, and when we are searching for subsequent CSes, we only
have to search up until where the previous unique buffers were.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-12 19:00:19 +00:00
Ilia Mirkin 48f04862c1 nvc0: set the render condition in the compute object
Fixes GL45-CTS.compute_shader.conditional-dispatching

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2017-02-11 21:06:52 -05:00
Ilia Mirkin 7e75f0913a gm107/ir: fix address offset bitfield for ATOMS
Fixes GL45-CTS.compute_shader.atomic-case1 on Maxwell

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2017-02-11 21:06:41 -05:00
Ilia Mirkin b38aab50a0 nv50/ir: convert an ATOM.EXCH without a destination into a store
On SM35 there does not appear to be a way to emit a ATOM.EXCH with a
null destination. This should be functionally equivalent to a plain
store however, so just do that.

Fixes GL45-CTS.compute_shader.atomic-case2 on SM35.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-02-11 20:25:26 -05:00