Commit Graph

66752 Commits

Author SHA1 Message Date
Eric Anholt 7d8b79f398 vc4: Allow pairing of some instructions that disagree about the WS bit.
No difference on shader-db because we tend to have a lot of other
conflicts going on as well (like RADDR_A disagreements)
2014-12-05 16:27:06 -08:00
Matt Turner e36c6513ce configure.ac: Replace contraction to fix syntax highlighting. 2014-12-05 13:22:56 -08:00
Ben Widawsky f13870db09 i965/gs: Avoid DW * DW mul
The GS has an interesting use for mul. Because the GS can emit multiple
vertices per input vertex, and it also has a unique count at the top of the URB
payload, the GS unit needs to be able to dynamically specify URB write offsets
(relative to the global offset). The documentation in the function has a very
good explanation from Paul on the mechanics.

This fixes around 2000 piglit tests on BSW.

v2:
Reworded commit message (Ben) no mention of CHV (Matt)
Change SHRT_MAX to USHRT_MAX (Ken, and Matt)
Update comment in code to reflect the use of UW (Ben)
Add Gen7+ assertion for the relevant GS code, since it won't work on Gen6- (Ken)
Drop the bogus hunk in emit_control_data_bits() (Ken)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84777 (with many dupes)
Cc: "10.4 10.3 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-05 12:12:46 -08:00
Eric Anholt 6f32deb538 vc4: Add separate write-after-read dependency tracking for pairing.
If an operation is the last one to read a register, the instruction
containing it can also include the op that has the next write to that
register.

total instructions in shared programs: 57486 -> 56995 (-0.85%)
instructions in affected programs:     43004 -> 42513 (-1.14%)
2014-12-05 10:53:53 -08:00
Eric Anholt 042962df2d vc4: Fix inverted priority of instructions for QPU scheduling.
We were scheduling TLB operations as early as possible, and texture setup
as late as possible.  When I introduced prioritization, I visually
inspected that an independent operation got moved above texture results
collection, which tricked me into thinking it was working (but it was just
because texture setup was being pushed late).

total instructions in shared programs: 57651 -> 57486 (-0.29%)
instructions in affected programs:     18532 -> 18367 (-0.89%)
2014-12-05 10:43:14 -08:00
Eric Anholt bd4057a5d7 vc4: Refuse to merge two ops that both access shared functions.
Avoids assertion failures in vc4_qpu_validate.c if we happen to find the
right set of operations available.
2014-12-05 10:43:14 -08:00
Eric Anholt dadc32ac80 vc4: Allow dead code elimination of color reads.
This might happen if the blending functions are set up to not actually use
the destination color/alpha, for example.
2014-12-05 10:43:14 -08:00
Eric Anholt 34cf86bdc4 vc4: Add a debug flag for waiting for sync on submit.
This is nice when you're tracking down which command list is hanging the
GPU.
2014-12-05 10:43:14 -08:00
Matt Turner c0e26c5d27 i965/fs: Move brw_file_from_reg() higher in the file.
This was supposed to be part of the previous commit.
2014-12-05 09:53:35 -08:00
Matt Turner db186f2a38 i965/fs: Make brw_reg_from_fs_reg static and remove prototype.
And move it above its first use in brw_fs_generator.cpp.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-05 09:49:42 -08:00
Matt Turner 2881b123d0 i965: Use ~0 to represent true on all generations.
Jason realized that we could fix the result of the CMP instruction on
Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4
backend before use, rather than when the bool was created. The FS does
this and it saves some unnecessary resolves.

On Ironlake:

total instructions in shared programs: 4289762 -> 4287277 (-0.06%)
instructions in affected programs:     619430 -> 616945 (-0.40%)

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-05 09:49:42 -08:00
Matt Turner 05e2578cac i965: Change the type of booleans to D.
This is a revert of commit 4656c14e ("i965/fs: Change the type of
booleans to UD and emit correct immediates") plus some small additional
fixes, like casting ctx->Const.UniformBooleanTrue to int and changing UD
to D in the ir_unop_b2f cases. Note that it's safe to leave 0x3f800000
as UD and as a literal it's more recognizable than 1065353216.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-05 09:49:42 -08:00
Matt Turner 66cc8de042 i965/fs: Add a negate() function.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-05 09:49:42 -08:00
Matt Turner 15f6118b77 i965/vec4: Don't DCE flag-writing insts because dest was unused.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-05 09:49:42 -08:00
Matt Turner 0d3cc01b0b i965/vec4: Allow CSE on uniform-vec4 expansion MOVs.
Three source instructions cannot directly source a packed vec4 (<0,4,1>
regioning) like vec4 uniforms, so we emit a MOV that expands the vec4 to
both halves of a register.

If these uniform values are used by multiple three-source instructions,
we'll emit multiple expansion moves, which we cannot combine in CSE
(because CSE emits moves itself).

So emit a virtual instruction that we can CSE.

Sometimes we demote a uniform to to a pull constant after emitting an
expansion move for it. In that case, recognize in opt_algebraic that if
the .file of the new instruction is GRF then it's just a real move that
we can copy propagate and such.

total instructions in shared programs: 5822418 -> 5812335 (-0.17%)
instructions in affected programs:     351841 -> 341758 (-2.87%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-12-05 09:49:42 -08:00
Matt Turner be80f69ecd glsl: Optimize scalar all_equal/any_nequal into equal/nequal.
Cuts an instruction from two shaders in Tesseract, by allowing the
(x+y) cmp 0 -> x cmp -y optimization to take place.

instructions in affected programs:     1198 -> 1194 (-0.33%)

Reviewed-by: Eric Anholt <eric@anholt.net>
2014-12-05 09:49:42 -08:00
José Fonseca a1fc6a91e5 mesa: Ensure stack is realigned on x86.
Nowadays GCC assumes stack pointer is 16-byte aligned even on 32-bits,
but that is an assumption OpenGL drivers (or any dynamic library for
that matter) can't afford to make as there are many closed- and open-
source application binaries out there that only assume 4-byte stack
alignment.

This fix uses force_align_arg_pointer GCC attribute, and is only a
stop-gap measure.

The right fix would be to pass -mstackrealign or
-mincoming-stack-boundary=2 to all source fails that use any -msse*
option, as there is no way to guarantee if/when GCC will decide to spill
SSE registers to the stack.

https://bugs.freedesktop.org/show_bug.cgi?id=86788

Reviewed-by: Brian Paul <brianp@vmware.com>
2014-12-05 15:17:37 +00:00
José Fonseca f9098f0972 util/primconvert: Avoid point arithmetic; apply offset on all cases.
Matches what u_vbuf_get_minmax_index() does.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-12-05 14:44:16 +00:00
Ilia Mirkin c3bed13604 util/primconvert: take ib offset into account
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
2014-12-05 07:23:48 -05:00
Ilia Mirkin fb434e675f util/primconvert: support instanced rendering
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
2014-12-05 07:23:48 -05:00
Ilia Mirkin 1dfa039168 util/primconvert: pass index bias through
The index_bias (aka base_vertex) applies to the downstream draw just as
much, since the actual index values are never modified.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
2014-12-05 07:23:48 -05:00
Kenneth Graunke ae45a5a28d i965: Compute VS attribute WA bits earlier and check if they changed.
BRW_NEW_VERTICES is flagged every time we draw a primitive.  Having
the brw_vs_prog atom depend on BRW_NEW_VERTICES meant that we had to
compute the VS program key and do a program cache lookup for every
single primitive.  This is painfully expensive.

The workaround bit computation is almost entirely based on the vertex
attribute arrays (brw->vb.inputs[i]), which are set by brw_merge_inputs.
The only thing it uses the VS program for is to see which VS inputs are
actually read.  brw_merge_inputs() happens once per primitive, and can
safely look at the currently bound vertex program, as it doesn't change
in the middle of a draw.

This patch moves the workaround bit computation to brw_merge_inputs(),
right after assigning brw->vb.inputs[i], and stores the previous WA bit
values in the context.  If they've actually changed from the last draw
(which is uncommon), we signal that we need a new vertex program,
causing brw_vs_prog to compute a new key.

Improves performance in Gl32Batch7 by 13.6123% +/- 0.739652% (n=166)
on Haswell GT3e.  I'm told Baytrail shows similar gains.

v2: Introduce a new BRW_NEW_VS_ATTRIB_WORKAROUNDS dirty bit, rather
    than reusing BRW_NEW_VERTEX_PROGRAM (suggested by Chris Forbes).
    This prevents unnecessary re-emission of surface/sampler related
    atoms (and an SOL atom on Sandybridge).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-12-04 17:50:52 -08:00
Matt Turner 0b4a688691 egl/dri2: Log a warning if no platforms are enabled.
If you hit this, you didn't compile with --with-egl-platforms=...

Recompile with something like --with-egl-platforms=x11,drm and make
clean and make again.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-12-04 15:13:51 -08:00
Kenneth Graunke ca19e89d6e i965: Drop BRW_NEW_VERTEX_PROGRAM and _NEW_TRANSFORM from Gen4 VS state.
These stopped being necessary in commit ab973403e4.

v2: Update commit message with a better explanation (thanks to Eric
    Anholt for doing the git archaeology).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-04 15:04:35 -08:00
Kenneth Graunke a2dd8ea59a i965: Drop BRW_NEW_VERTEX_PROGRAM from Gen7+ 3DSTATE_VS atoms.
We don't access brw->vertex_program or ctx->_Shader since the previous
commit, so we don't need this dirty bit.

I think it's still necessary on Gen6 because it still conflates
constant uploading with unit state uploading.  We can fix that later.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-04 15:04:35 -08:00
Kenneth Graunke 7b6620faf5 i965: Store floating point mode choice in brw_stage_prog_data.
We use IEEE mode for GLSL programs, but need to use ALT mode for ARB
programs so that 0^0 == 1.  The choice is based entirely on the shader
source language.

Previously, our code to determine which mode we wanted was duplicated
in 8 different places (VS and FS for Gen4-5, Gen6, Gen7, and Gen8).
The ctx->_Shader->CurrentProgram[stage] == NULL check was confusing
as well - we use CurrentProgram (non-derived state), but _Shader
(derived state).  It also relies on knowing that ARB programs don't
use gl_shader_program structures today.  The compiler already makes
this assumption in a few places, but I'd rather keep that assumption
out of the state upload code.

With this patch, we select the mode at compile time, and store that
choice in prog_data.  The state upload code simply uses that decision.

This eliminates a BRW_NEW_*_PROGRAM dependency in the state upload code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-04 15:04:35 -08:00
Kenneth Graunke d300e58db0 i965: Make Gen4-5 and Gen8+ ALT checks use ctx->_Shader too.
Commit c0347705 changed the Gen6-7 code to use ctx->_Shader rather than
ctx->Shader, but neglected to change the Gen4-5 or Gen8+ code.

This might fix SSO related bugs, but ALT mode is only used for ARB
programs, so if there's an actual problem, it's likely no one would
run into it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-04 15:04:35 -08:00
Kenneth Graunke 8daf3c53c7 i965: Move PSCDEPTH calculations from draw time to compile time.
The "Pixel Shader Computed Depth Mode" value is entirely based on the
shader program, so we can easily do it at compile time.  This avoids the
if+switch on every 3DSTATE_WM (Gen7)/3DSTATE_PS_EXTRA (Gen8+) upload,
and shares a bit more code.

This also simplifies the PMA stall code, making it match the formula
more closely, and drops a BRW_NEW_FRAGMENT_PROGRAM dependency.  (Note
that the previous comment was wrong - the code and the documentation
have != PSCDEPTH_OFF, not ==.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-04 15:04:35 -08:00
Rob Clark 4265148ac6 freedreno/a4xx: unify vertex/texture formats into a single table
Similar to the scheme that Ilia put in place for a3xx.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-12-04 16:01:37 -05:00
Rob Clark e9589a8fcf freedreno/a4xx: fd4_util -> fd4_format
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-12-04 16:01:37 -05:00
Rob Clark 8bf69a29bb freedreno: update generated headers / a4xx fmt rename
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-12-04 16:01:37 -05:00
Kenneth Graunke bcc7eb115e i965: Add var->location != -1 assertions.
We shouldn't receive variables with invalid locations set - adding these
assertions should help catch problems before they cause crashes later.

Inspired by similar code in st_glsl_to_tgsi.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-12-03 17:45:16 -08:00
Matt Turner b5b18e4687 i965/fs: Don't offset uniform registers in half().
Half gives you the second half of a SIMD16 register, but if the register
is a uniform it would incorrectly give you the next register.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-03 16:47:45 -08:00
Rob Clark c74f2db0a5 freedreno/a4xx: frag-depth fixes
Also seems to fix kill/discard.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-12-03 16:38:26 -05:00
Ian Romanick a909b995d9 linker: Assign varying locations geometry shader inputs for SSO
Previously only geometry shader outputs would be assigned locations if
the geometry shader was the only stage in the linked program.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: pavol@klacansky.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82585
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-12-03 11:33:49 -08:00
Ian Romanick 5eca78a00a linker: Wrap access of producer_var with a NULL check
producer_var could be NULL if consumer_var is not NULL and
consumer_is_fs is false.  This will occur when the producer is NULL and
the consumer is the geometry shader for a program that contains only a
geometry shader.  This will occur starting with the next patch.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: pavol@klacansky.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82585
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-12-03 11:33:49 -08:00
Jan Vesely a2f2eebfdf st/xvmc: Fix compiler warnings
Mostly signed/unsigned comparison

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Christian König <christian.koenig@amd.com>
2014-12-03 17:07:08 +01:00
Axel Davy 712a4c5438 st/nine: Fix vertex declarations for non-standard (usage/index)
Nine code to match vertex declaration to vs inputs was limiting
the number of possible combinations.

Some sm3 games have issues with that, because arbitrary (usage/index)
can be used.

This patch does the following changes to fix the problem:
. Change the numbers given to (usage/index) combinations to uint16
. Do not put limits on the indices when it doesn't make sense
. change the conversion rule (usage/index) -> number to fit all combinations
. Instead of having a table usage_map mapping a (usage/index) number to
an input index, usage_map maps input indices to their (usage/index)

Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Tested-by: Yaroslav Andrusyak <pontostroy@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2014-12-03 16:39:24 +01:00
Axel Davy 5d6d260833 st/nine: sm1_declusage_to_tgsi, do not restrict indices with TGSI_SEMANTIC_GENERIC
With sm3, you can declare an input/output with an usage and an usage index.

Nine code hardcodes the translation usage/index to a corresponding TGSI code.
The translation was limited to a few usage/index combinations that were corresponding
to most of the needs of games, but some games did not work.

This patch rewrites that Nine code to map all possible usage/index combination
to TGSI code. The index associated to TGSI_SEMANTIC_GENERIC doesn't need to be low
for good performance, as the old code was supposing, and is not particularly bounded
(it's UINT16). Given the index is BYTE, we can map all combinations.

Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Tested-by: Yaroslav Andrusyak <pontostroy@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2014-12-03 16:39:24 +01:00
Axel Davy 3e1f731d3e st/nine: Queries: Always return D3D_OK when issuing with D3DISSUE_BEGIN
This is the behaviour that Wine tests.

Reviewed-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2014-12-03 16:39:24 +01:00
Axel Davy 2f78259c11 st/nine: Queries: always succeed for D3DQUERYTYPE_TIMESTAMP when flushing
This is the behaviour that Wine tests

Tested-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2014-12-03 16:39:24 +01:00
Axel Davy 225d7f8e0e st/nine: Queries: allow app to call GetData without Issuing first
Nine was allowing that behaviour, but was not filling the result.

Tested-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2014-12-03 16:39:24 +01:00
Axel Davy eac0b9b68a st/nine: Queries: Fix D3DISSUE_END behaviour.
Issuing D3DISSUE_END should:
. reset previous queries if possible
. end the query

Previous behaviour wasn't calling end_query for
queries not needing D3DISSUE_BEGIN, nor resetting
previous queries.

This fixes several applications not launching properly.

Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Tested-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2014-12-03 16:39:24 +01:00
Axel Davy ca0588d1a1 st/nine: Queries: return S_FALSE instead of INVALIDCALL when in building query state
It is the same behaviour as wine has.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2014-12-03 16:39:24 +01:00
Axel Davy b0302a95ec st/nine: Queries: Use gallium caps to get if queries are supported. (v2)
Some queries need the driver to advertise a cap to be supported.
For example r300 doesn't support them.

v2 (David): check also for PIPE_CAP_QUERY_PIPELINE_STATISTICS, fix wine
            tests on r300g

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2014-12-03 16:39:24 +01:00
Axel Davy 6b35662e30 st/nine: Queries: Remove flush logic
get_query_result flushes automatically, we don't need to flush.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2014-12-03 16:39:24 +01:00
Axel Davy 3e48791aea st/nine: Queries: remove dummy queries
Applications are supposed to call CreateQuery with a NULL
ppQuery to know if the query is supported. We supported that.

However when ppQuery was not NULL, we were accepting to create the
query and were creating a dummy query even when the query is not
supported.

Wine has different behaviour. This patch drops the dummy queries
support and matches wine behaviour.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2014-12-03 16:39:23 +01:00
Ilia Mirkin 79f9a106b9 freedreno/a3xx: implement anisotropic filtering
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-12-03 09:23:46 -05:00
Rob Clark b491d1ca6e freedreno/a4xx: rect textures
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-12-03 09:22:05 -05:00
Rob Clark fbba633f2f freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-12-03 09:22:05 -05:00