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Author SHA1 Message Date
Marek Olšák 71794567f9 radeonsi: remove tabs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 428360662f radeonsi: don't add the tess ring buffers into the cs_preamble state 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 1c1d34a67a radeonsi: rename init_config states to cs_preamble states 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák bbc0a2d51d radeonsi: don't add the border color buffer into the init_config state 
We might have to replace init_config for preemption.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák f8e8701cf1 radeonsi: replace ctx->screen with sscreen in si_flush_gfx_cs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5506>
 2020-06-23 09:12:16 +00:00
Marek Olšák 470b319813 radeonsi: don't wait for idle at the end of gfx IBs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5506>
 2020-06-23 09:12:16 +00:00
Marek Olšák caeb44aa24 radeonsi: split si_all_descriptors_begin_new_cs and rename functions 
A future commit will extend it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:45:07 -04:00
Marek Olšák 7b6b35c6b5 radeonsi: move resetting tracked registers into a new function 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:45:07 -04:00
Marek Olšák 56af131f33 Revert "radeonsi: don't wait for idle at the end of gfx IBs" 
This reverts commit 266fec1307.

The kernel doesn't wait for idle as part of implicit sync.

Fixes: 266fec1307
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2950

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:44:44 -04:00
Marek Olšák 8c9b9aac7d gallium: change comments to remove 'state tracker' 
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4902>
 2020-05-13 13:47:27 -04:00
Marek Olšák 266fec1307 radeonsi: don't wait for idle at the end of gfx IBs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4894>
 2020-05-05 11:52:21 -04:00
Pierre-Eric Pelloux-Prayer d7008fe46a radeonsi: switch to 3-spaces style 
Generated automatically using clang-format and the following config:

AlignAfterOpenBracket: true
AlignConsecutiveMacros: true
AllowAllArgumentsOnNextLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: false
AlwaysBreakAfterReturnType: None
BasedOnStyle: LLVM
BraceWrapping:
  AfterControlStatement: false
  AfterEnum: true
  AfterFunction: true
  AfterStruct: false
  BeforeElse: false
  SplitEmptyFunction: true
BinPackArguments: true
BinPackParameters: true
BreakBeforeBraces: Custom
ColumnLimit: 100
ContinuationIndentWidth: 3
Cpp11BracedListStyle: false
Cpp11BracedListStyle: true
ForEachMacros:
  - LIST_FOR_EACH_ENTRY
  - LIST_FOR_EACH_ENTRY_SAFE
  - util_dynarray_foreach
  - nir_foreach_variable
  - nir_foreach_variable_safe
  - nir_foreach_register
  - nir_foreach_register_safe
  - nir_foreach_use
  - nir_foreach_use_safe
  - nir_foreach_if_use
  - nir_foreach_if_use_safe
  - nir_foreach_def
  - nir_foreach_def_safe
  - nir_foreach_phi_src
  - nir_foreach_phi_src_safe
  - nir_foreach_parallel_copy_entry
  - nir_foreach_instr
  - nir_foreach_instr_reverse
  - nir_foreach_instr_safe
  - nir_foreach_instr_reverse_safe
  - nir_foreach_function
  - nir_foreach_block
  - nir_foreach_block_safe
  - nir_foreach_block_reverse
  - nir_foreach_block_reverse_safe
  - nir_foreach_block_in_cf_node
IncludeBlocks: Regroup
IncludeCategories:
  - Regex:           '<[[:alnum:].]+>'
    Priority:        2
  - Regex:           '.*'
    Priority:        1
IndentWidth: 3
PenaltyBreakBeforeFirstCallParameter: 1
PenaltyExcessCharacter: 100
SpaceAfterCStyleCast: false
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: false
SpacesInContainerLiterals: false

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
 2020-03-30 11:05:52 +00:00
Marek Olšák 8db00a51f8 radeonsi/gfx10: implement NGG culling for 4x wave32 subgroups 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-20 16:16:11 -05:00
Marek Olšák aa2d846604 radeonsi/gfx10: move GE_PC_ALLOC setting to shader states 
The value is not changed. I just use a different way to compute it.

The value will vary with NGG culling.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-20 16:16:11 -05:00
Marek Olšák fd84e422b6 radeonsi: clean up messy si_emit_rasterizer_prim_state 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 15:48:49 -05:00
Marek Olšák 991328498b radeonsi: move SI and CIK+ SDMA code into 1 common function for cleanups 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
 2020-01-06 15:38:35 -05:00
Marek Olšák 3c265c2586 radeonsi: rename dma_cs -> sdma_cs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
 2020-01-06 15:38:33 -05:00
Timothy Arceri 1909bc526d util: remove LIST_IS_EMPTY macro 
Just use the inlined function directly. The new function was introduced
in addcf410.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
 2019-10-28 11:24:39 +00:00
Marek Olšák 438ede3ca3 radeonsi: call the reset callback if get_device_reset_status returns a failure 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-10-17 14:56:24 -04:00
Marek Olšák 4dde40908f radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flags 
We need two different values of the register, one for NGG and one for
legacy, in order to fix edge flags for the legacy pipeline.

Passing the ngg flag to emit_clip_regs would be too complicated,
so CONTEXT_REG_RMW is used for partial register updates.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Samuel Pitoiset d62d2840c4 ac: add has_clear_state to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:05 +02:00
Marek Olšák 91227a1e17 radeonsi/gfx10: add global use_ngg and use_ngg_streamout flags 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:09:02 -04:00
Marek Olšák 16392cc3f3 radeonsi/gfx10: fix and enable CLEAR_STATE 
it was a driver bug.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-07-23 15:03:47 -04:00
Marek Olšák d7e80ba1e7 radeonsi: set FLUSH_ON_BINNING_TRANSITION when needed 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
 2019-07-09 17:24:16 -04:00
Marek Olšák b680f723f8 radeonsi/gfx10: export correct PrimitiveID from NGG vertex shaders 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:13 -04:00
Marek Olšák 6920f09f4b radeonsi/gfx10: fix GL_LINE polygon mode for decomposed primitives 
We need to tell PA to accept edge flags generated by the input assembler,
because decomposed primitives shouldn't draw inner edges.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:13 -04:00
Marek Olšák 6944f99176 radeonsi/gfx10: allocate GDS BOs for streamout 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:13 -04:00
Marek Olšák 395185912d radeonsi/gfx10: make sure GDS is idle between IBs 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:13 -04:00
Nicolai Hähnle 5ff3aff0d6 radeonsi/gfx10: implement streamout 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:13 -04:00
Nicolai Hähnle 77e715541c radeonsi/gfx10: emit VGT_GS_OUT_PRIM_TYPE from draw and add it to VS_STATE 
With NGG, the VGT_GS_OUT_PRIM_TYPE can change without a shader change.

The VS_STATE is required for both streamout and culling from a vertex
shader without pre-compiling outprim-specific variants.

We could consider compiling specialized variants in the future. We
could also consider compiling the NGG logic as an epilog.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 0c6c6810bd radeonsi/gfx10: add si_context::emit_cache_flush 
The introduction of GCR_CNTL makes cache flush handling on gfx10
sufficiently different that it makes sense to just use a separate
function.

Since emit_cache_flush is called quite early during context init,
we initialize the pointer explicitly in si_create_context.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Marek Olšák 1d6e358c36 radeonsi: rename and re-document cache flush flags 
SMEM and VMEM caches are L0 on gfx10.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-06-24 21:04:10 -04:00
Marek Olšák c9b7a37b8f radeonsi: cull primitives with async compute for large draw calls 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2019-05-16 13:13:34 -04:00
Marek Olšák 187f1c999f winsys/amdgpu: add REWIND emulation via INDIRECT_BUFFER into cs_check_space 
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2019-05-16 13:10:07 -04:00
Marek Olšák ccfcb9d818 ac: rename SI-CIK-VI to GFX6-GFX7-GFX8 
Acked-by: Dave Airlie <airlied@redhat.com>

We already use GFX9 and I don't want us to have confusing naming
in the driver. GFXn naming is better from the driver perspective,
because it's the real version of the gfx portion of the hw. Also,
CIK means Bonaire-Kaveri-Kabini, it doesn't mean CI.

It shouldn't confuse our SDMA, UVD, VCE etc. code much. Those have
nothing to do with GFXn and they have their own version numbers.
 2019-05-15 20:54:10 -04:00
Marek Olšák 383f406591 radeonsi: remove dirty slot masks from scissor and viewport states 
All registers in the array need to be updated if any of them is changed.

Only apps writing gl_ViewportIndex were affected by this bug.
 2019-04-25 11:49:38 -04:00
Marek Olšák 951d60f8cd radeonsi: delay adding BOs at the beginning of IBs until the first draw 
so that bound compute shader resources won't be added when they are not
needed and same for graphics.

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2019-04-23 11:36:36 -04:00
Marek Olšák 09bb8c8557 radeonsi: add helper si_get_minimum_num_gfx_cs_dwords 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2019-04-23 11:36:34 -04:00
Marek Olšák a1378639ab radeonsi: always use compute rings for clover on CI and newer (v2) 
initialize all non-compute context functions to NULL.

v2: fix SI
 2019-02-26 14:58:55 -05:00
Marek Olšák edbd2c1ff5 radeonsi: use SDMA for uploading data through const_uploader 
v2: use tc.stream_uploader in si buffer_transfer_map if not called from
    the driver thread

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2019-02-20 21:04:29 -05:00
Marek Olšák 501ff90a95 radeonsi: rename r600_resource -> si_resource 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-01-22 13:32:18 -05:00
Marek Olšák 1cfbed7587 radeonsi: remove r600 from comments 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-01-22 12:26:45 -05:00
Marek Olšák 4fd8d2df9c radeonsi: move emission of PA_SU_VTX_CNTL into emit_guardband 
We'll modify the quant mode there, which also affects the guarband
computation.
 2018-10-16 15:28:22 -04:00
Marek Olšák b94824c787 radeonsi: set PA_SU_PRIM_FILTER_CNTL optimally 2018-10-16 15:28:22 -04:00
Marek Olšák 9e182b8313 radeonsi: center viewport to improve guardband clipping for high resolutions 
This will be more useful when we change the quant mode to increase subpixel
precision and decrease the viewport range (which might not be possible
if the viewport is not centered in the viewport range).
 2018-10-16 15:28:22 -04:00
Sonny Jiang 084cf3b966 radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuse 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-10-05 19:04:13 -04:00
Sonny Jiang ce1d72609d radeonsi:optimizing SET_CONTEXT_REG for shaders Tessellation 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-10-05 19:04:13 -04:00
Sonny Jiang 4de328da07 radeonsi:optimizing SET_CONTEXT_REG for shaders PS 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-10-05 19:04:13 -04:00
Sonny Jiang f243980f2c radeonsi:optimizing SET_CONTEXT_REG for shaders VS 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-10-05 19:04:13 -04:00
Sonny Jiang 4052624398 radeonsi:optimizing SET_CONTEXT_REG for shaders GS 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-10-05 19:04:13 -04:00