We already throw out any variables which may have a complex use so we
just need to make sure that our mode checks don't assert if we have a
deref which may_be but not must_be nir_var_function_temp.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9068>
We can't move the shuffle to a new block so this only works if the
shuffle and the bcsel are in the same block. Fortunately, in the
motivating case, this is true.
Also, we have to be careful around discard. We could try really hard to
just avoid moving them past discard but we choose to simply bail if we
see a discard instead.
Fixes: 4ff4d4e569 "nir/opt_intrinsic: Optimize bcsel(b, shuffle..."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9068>
The nvc0 nouveau backend already claimed to support format modifiers, but
in practice it ignored them when allocating buffers outside of a
perfunctory check for the linear modifier in the first element of the
format modifier list.
This change deduces the supported modifiers, if any, for a given miptree
creation request, prioritizes them based on performance and memory waste
properties, compares the requested modifiers against the prioritized list
of supported modifiers, and overrides the internal layout calculations
based on the layout defined by the resulting modifier.
Additionally, if modifiers are provided and none are compatible with the
miptree creation request, the function now fails. This brings the nouveau
behavior in line with other drivers such as i965 and etnaviv.
Signed-off-by: James Jones <jajones@nvidia.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3724>
Other drivers fail resource allocation when a list of modifiers for the
resource is provided but none are supported. This includes cases when the
never-supported DRM_FORMAT_MOD_INVALID modifier is explicitly passed. To
enable matching that functionality in nouveau, use an empty modifier list
rather than creating a one-entry list containing only
DRM_FORMAT_MOD_INVALID when the non-modifier resource creation function is
used.
This change stops short of failing allocations when no modifier is
specified, because the current code ignores all modifiers except the linear
modifier when creating resources, so there is not yet a framework in place
to determine which modifiers are valid for a given resource creation
request, and hence no way to reject only those which are invalid.
Signed-off-by: James Jones <jajones@nvidia.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3724>
Replace existing usage of the NVIDIA_16BX2_BLOCK format modifiers with
parameterized use of the more general macro. Nouveau will now report
support for slightly different modifiers depending on whether the
underlying chip is a tegra GPU or not, and will potentially report valid
format modifiers for more resource types, but overall this should be a
functional no-op for existing applications.
Signed-off-by: James Jones <jajones@nvidia.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3724>
Older Tegra GPUs use a different sector bit swizzling layout than desktop
and Xavier GPUs. Hence their format modifiers must be differentiated from
those of other GPUs. As a precursor to supporting more expressive block
linear format modifiers, deduce the sector layout used for a given GPU from
its chipset and stash the layout in the nouveau screen structure.
Signed-off-by: James Jones <jajones@nvidia.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3724>
this writes the pipeline cache to disk on shutdown
ideally we'd rather write this incrementally any time we make a new pipeline,
but that ends up breaking the disk cache infrastructure since we're always writing
to the same file, so this is the best we can do for now
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9094>
Draw-time variants are still synchronous, but I'm not sure there is much
(easy) benefit from generating them asynchronously. Without patching
the cmdstream later before batch submit, we'd end up waiting for them
immediately. But we should mostly only hit draw-time variants for
desktop GL (and mostly legacy features).
Note: new xfb xfail on a5xx, but most of the xfb tests are already xfail
so I think we just managed to change the timing a bit, rather than this
being related to async compile.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3857
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
There was just a single remaining caller of ir3_shader_create_compute(),
so fold that into ir3_shader_compute_state_create().
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
This had only a single caller, so no need to be exported. With
that done, fold the ir3_shader creation (ie. the cheap part) into
ir3_shader_state_create(), and rename what is left.
This is prep to moving initial variant creation to a work queue.
It does slightly change the error handling, in that we don't
cleanup the shader hwcso. We wouldn't be able to do this anyways
with async compile. But it ends up using the same error handling
paths that we'd hit if we got a compile failure for a draw-time
variant.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
All the ir3 using backends already call ir3_screen_init(), so lets just
move compiler creation there.
In a subsequent patch, we'll add initialization of the queue for async
compile.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
These were identical between a5xx and a6xx, so move into shared helper
that can be directly plugged into pctx, similar to the various 3d shader
state creation.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
Previously, when we had a prototype-only function in SPIR-V, we would
compile it just fine and the function would have an impl that did
nothing. This commit changes that so that the nir_function::impl is
NULL to indicate a prototype-only function.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9069>
Incase of error returns missed the free calls for config and context.
This patch handling in freeing them
Signed-off-by: SureshGuttula <sguttula@amd.com>
Reviewed-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8993>
the logic for this was broken and failed to detect any extensions other
than the first one listed. instead, we must follow this logic chain:
1. check the extension name
2a. if this is an extension that got promoted to core, check the @since version
3a. if current version >= @since version
4a. if the extension has required features/properties, check those
4b. else set supported
3b. else
4a. if the extension has required features/properties, check those
4b. else set supported
2b. else
4a. if the extension has required features/properties, check those
4b. else set supported
Fixes: efe6f00e34 ("zink/codegen: do not enable extensions that are now core")
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9081>
There are a bunch of cases where we can pretty quickly determine that
the high bits don't matter. In these cases, delete the casts.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8872>
This add support for the Intel Apollo Lake and Gemini Lake families,
however the job will be disabled by default unless the developer
manually hit play for the iris-apl-traces and iris-glk-traces jobs in
GitLab CI.
These devices are still under experimental level support in
the Lava lab and are not guaranteed to work reliably yet. Once they
become reliable and more resilient we will enable them by default in
MesaCI.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8162>
For now we will start with iris. Our main focus is to enable the devices
to be used in MesaCI.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8162>
Ensure that all resources are properly released by
properly parenting them to a memory context and releasing
the context during test teardown.
Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8162>
Multiply by the destination bit size to get the number of bits to
load instead of assuming 32 bits.
Fixes: 2e57684d2d ("pan/bi: Implement load_ubo with the builder")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9071>
Instructions are allowed to access up to two rf registers, or one rf
register and a small immediate. This change allows qpu_merge_inst to
take full advantage of this by allowint the merging of two instructions
if they have no more than two different rf registers between them,
or one rf register and one small immediate. qpu_merge_inst rewrites
the instructions as needed to pack everything into raddr_a and raddr_b
in the merged instruction.
shader-db stats:
total instructions in shared programs: 19938769 -> 18929664 (-5.06%)
instructions in affected programs: 17929438 -> 16920333 (-5.63%)
helped: 95008
HURT: 242
helped stats (abs) min: 1 max: 785 x̄: 10.62 x̃: 7
helped stats (rel) min: 0.30% max: 21.25% x̄: 5.37% x̃: 4.98%
HURT stats (abs) min: 1 max: 2 x̄: 1.10 x̃: 1
HURT stats (rel) min: 0.30% max: 3.12% x̄: 1.62% x̃: 1.54%
95% mean confidence interval for instructions value: -10.67 -10.52
95% mean confidence interval for instructions %-change: -5.37% -5.33%
Instructions are helped.
total max-temps in shared programs: 3122664 -> 3112446 (-0.33%)
max-temps in affected programs: 124881 -> 114663 (-8.18%)
helped: 5445
HURT: 0
helped stats (abs) min: 1 max: 15 x̄: 1.88 x̃: 1
helped stats (rel) min: 1.49% max: 40.54% x̄: 8.97% x̃: 6.67%
95% mean confidence interval for max-temps value: -1.91 -1.84
95% mean confidence interval for max-temps %-change: -9.12% -8.81%
Max-temps are helped.
total sfu-stalls in shared programs: 38028 -> 41231 (8.42%)
sfu-stalls in affected programs: 6053 -> 9256 (52.92%)
helped: 664
HURT: 3380
helped stats (abs) min: 1 max: 2 x̄: 1.04 x̃: 1
helped stats (rel) min: 9.09% max: 100.00% x̄: 70.81% x̃: 100.00%
HURT stats (abs) min: 1 max: 4 x̄: 1.15 x̃: 1
HURT stats (rel) min: 0.00% max: 300.00% x̄: 46.39% x̃: 25.00%
95% mean confidence interval for sfu-stalls value: 0.76 0.82
95% mean confidence interval for sfu-stalls %-change: 25.03% 29.26%
Sfu-stalls are HURT.
total inst-and-stalls in shared programs: 19976797 -> 18970895 (-5.04%)
inst-and-stalls in affected programs: 17963129 -> 16957227 (-5.60%)
helped: 95017
HURT: 245
helped stats (abs) min: 1 max: 785 x̄: 10.59 x̃: 7
helped stats (rel) min: 0.30% max: 21.25% x̄: 5.35% x̃: 4.95%
HURT stats (abs) min: 1 max: 2 x̄: 1.09 x̃: 1
HURT stats (rel) min: 0.30% max: 3.12% x̄: 1.61% x̃: 1.54%
95% mean confidence interval for inst-and-stalls value: -10.64 -10.48
95% mean confidence interval for inst-and-stalls %-change: -5.35% -5.31%
Inst-and-stalls are helped.
v2 (Iago):
- moved early return for naddrs > 2 even earlier.
- only update {add,mul}.b mux if instruction has more than one operand.
- don't OR b->raddr_{a,b} if we are not merging add/mul instructions.
- don't initialize packed to 0.
- minor style fixes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9026>
Jason Ekstrand
James Jones
Mike Blumenkrantz
Rob Clark
Jesse Natalie
Jason Ekstrand
SureshGuttula
Rohan Garg
Thong Thai
Gustavo Padovan
Icecream95
Bas Nieuwenhuizen
Arcady Goldmints-Orlov
Michel Zou