3d145ec7f1
zink: use global image rebind counter for dmabuf export
...
this is a bit less flimsy and handles more than just framebuffer rebinds
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16476 >
2022-05-20 16:42:21 +00:00
b181080d9f
zink: move renderpass handling to zink_render_pass.c
...
no functional changes
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16476 >
2022-05-20 16:42:21 +00:00
4457a9388a
zink: use zink_batch_no_rp to end renderpasses
...
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16476 >
2022-05-20 16:42:21 +00:00
3e1cd9f623
zink: always use zink_batch_rp to init renderpass
...
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16476 >
2022-05-20 16:42:21 +00:00
9a03beb2e9
zink: rename a fb surface variables
...
no functional changes, just being more consistent
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16476 >
2022-05-20 16:42:21 +00:00
95d4e5435b
radv: export implicit primitive ID in NIR for legacy VS or TES
...
It's implicit for VS or TES, while it's required for GS or MS.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16404 >
2022-05-20 14:55:05 +00:00
d711e9813c
radv: determine if shaders use NGG before linking
...
This would be needed by some NIR pass during linking. Given that NGG
settings are currently dispatched in many places, I don't think this
should hurt but it should be refactored at some point.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16404 >
2022-05-20 14:55:05 +00:00
b90d7b9b38
broadcom/compiler: don't promote early fragment tests when writing sample mask
...
If the sample mask is being written it means we want to discard some of the
samples generated so we should not be promoting the fragment shader to
do early tests, since that would not take into account the sample mask
written from the shader.
Fixes:
dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_samples_4
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16626 >
2022-05-20 13:04:32 +00:00
a987167ebd
v3dv: fix format usage checks when extended usage flag is set
...
Fixes:
dEQP-VK.image.extended_usage_bit_compatibility.*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16625 >
2022-05-20 12:38:19 +00:00
2c420fcf40
v3dv: expose VK_KHR_vulkan_memory_model
...
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16602 >
2022-05-20 12:00:44 +00:00
f2635ca47b
turnip: add an assertion for max descriptor set count.
...
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16624 >
2022-05-20 09:49:00 +00:00
53445284a4
etnaviv: add linear PE support
...
GPUs with the LINEAR_PE feature bit have the ability to render into linear
buffers. While this decreases PE cache effectiveness and is thus slower than
rendering into a (super-)tiled buffer, it's still preferable for cases where
we would need a blit to get into linear otherwise, i.e. when importing a
linear buffer or when linear is forced on allocation by usage flags or
modifiers.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16615 >
2022-05-20 09:30:18 +00:00
8452bd7984
etnaviv: improve single buffer setup
...
The blob only switches to the 3 single buffer state when required, which seems
to be the case when any color or ZS target is <= 16bpp. Using 2 as the single
buffer state gives a very small 1-2% performance improvement on fillrate
constrained rendering, so it likely affects some PE cache setting.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16615 >
2022-05-20 09:30:18 +00:00
cbb81e09ee
winsys: Do not use Display type when X11 is not present in build
...
Reviewed-by: Adam Jackson <ajax@redhat.com>
Closes : mesa/mesa#6520
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16608 >
2022-05-20 09:06:41 +00:00
e87135c552
radeonsi/tests: use a smaller tests-per-group value
...
Faster glcts runs (44 -> 34 sec).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16580 >
2022-05-20 09:57:14 +02:00
c2892b811a
radeonsi/tests: add a --slow option
...
Some glcts tests implement tons of tests because they verify
every possible combination of format/swizzle/target/...
They take a long time to execute and aren't possible to run
using multiple processes.
The proper way to fix it would be to split them in vk-gl-cts,
as is already done for some of them (eg es31fTextureGatherTests.cpp).
In the meantime, not running them makes glcts run almost
10 times faster.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16580 >
2022-05-20 09:57:05 +02:00
5b2756ec2c
radv: fix assertion for the count of xfb output
...
It's an counter, not an index.
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16623 >
2022-05-20 06:43:11 +00:00
04459c8287
radv: Fix RTPSO hashing of pGroups.
...
There are padding bytes here. Only hash relevant members.
Fixes: ca2d96db51https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16582 >
2022-05-20 07:43:58 +02:00
b58dd252aa
lavapipe: Use the common BindVertexBuffers wrapper
...
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16611 >
2022-05-20 02:12:37 +00:00
a299e5efbb
radv: Use the common CmdBindVertexBuffers wrapper
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16611 >
2022-05-20 02:12:37 +00:00
50a00f889c
radv: Add a sqtt entrypoint for CmdBindVertexBuffers2
...
Fixes: b262284300https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16611 >
2022-05-20 02:12:37 +00:00
c24aa449d0
vulkan,anv,turnip: Add a common CmdBindVertexBuffers wrapper
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16611 >
2022-05-20 02:12:37 +00:00
cc4d5b1666
radeonsi: lower nir_intrinsic_sparse_residency_code_and
...
This is required by lower_tg4_offsets which split one
sparseTextureGatherOffsetsARB call to four sparseTextureGatherOffsetARB
calls and merge their resisident results into one.
Fixes: ee040a6b63https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16599 >
2022-05-20 01:45:12 +00:00
2fbbb8ad63
zink: update radv baseline
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16622 >
2022-05-19 23:51:38 +00:00
d6b943adde
egl: Fix EGL_EXT_platform_xcb name string to match the registry
...
Signed-off-by: Nicolas Caramelli <caramelli.devel@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16609 >
2022-05-19 23:21:15 +00:00
e6981d6da2
docs: update calendar and link releases notes for 22.0.4
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16617 >
2022-05-19 22:38:46 +00:00
f0e3c71c96
docs: Extend calendar entries for 22.0 by 1 releases.
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16617 >
2022-05-19 22:38:46 +00:00
569553f7c4
docs: add sha256sum to 22.0.4 notes
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16617 >
2022-05-19 22:38:46 +00:00
3cfcb3a1e0
docs: add release notes for 22.0.4
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16617 >
2022-05-19 22:38:46 +00:00
c6cddd2e17
lavapipe: Use the correct ICD path on Win32
...
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16612 >
2022-05-19 21:53:06 +00:00
27314718a3
intel: Drop Wa_1409226450 (stall before instruction cache invalidation)
...
Production Tigerlake and DG1 hardware shouldn't need this workaround.
It was only needed on the very first steppings which never went public.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16575 >
2022-05-19 21:31:45 +00:00
7938ce4af3
freedreno/ir3: Lower texture instructions used only for f2f16 to 16-bit.
...
2.5% improvement in gfxbench vk-5-normal. No obvious change on
gl-5-normal.
shader-db on Rob's android shaders:
total instructions in shared programs: 770644 -> 770595 (<.01%)
instructions in affected programs: 14880 -> 14831 (-0.33%)
total nops in shared programs: 167784 -> 167860 (0.05%)
nops in affected programs: 3351 -> 3427 (2.27%)
total non-nops in shared programs: 602860 -> 602735 (-0.02%)
non-nops in affected programs: 10523 -> 10398 (-1.19%)
total mov in shared programs: 19313 -> 19286 (-0.14%)
mov in affected programs: 365 -> 338 (-7.40%)
total cov in shared programs: 18075 -> 17978 (-0.54%)
cov in affected programs: 566 -> 469 (-17.14%)
total dwords in shared programs: 1612848 -> 1612596 (-0.02%)
dwords in affected programs: 13882 -> 13630 (-1.82%)
total last-baryf in shared programs: 56144 -> 55975 (-0.30%)
last-baryf in affected programs: 482 -> 313 (-35.06%)
total full in shared programs: 36094 -> 36092 (<.01%)
full in affected programs: 10 -> 8 (-20.00%)
total sstall in shared programs: 66986 -> 66923 (-0.09%)
sstall in affected programs: 1392 -> 1329 (-4.53%)
total systall in shared programs: 91244 -> 91072 (-0.19%)
systall in affected programs: 1194 -> 1022 (-14.41%)
total (sy) in shared programs: 4316 -> 4321 (0.12%)
(sy) in affected programs: 19 -> 24 (26.32%)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
1cf0736f1c
freedreno/ir3: Add support for 16-bit nir_texop_lod.
...
Same basic path, just do the rescaling in half float.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
a28d2e87d3
turnip: Make RelaxedPrecision-decorated ALU ops 16-bit.
...
Improves gfxbench vk-5-normal performance 5.5%.
Fixes : #6346
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
260559050a
spirv_to_nir: Cast RelaxedPrecision ALU op dests to mediump.
...
This is controlled by spirv_to_nir_options.relaxed_precision_alu, because
some drivers don't want it.
This gets us mostly 16-bit math on turnip in vk-5-normal.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
87d7431198
spirv: Use nir_vec_scalars() to simplify matrix transpose.
...
This should emit fewer instructions that need to be copy-propagated away.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
633cf4eca1
freedreno/ir3: Fix 16-bit bit_count.
...
No need to do the 16-bit lowering if it already is.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
1c077ca9c0
u_trace/anv/iris: drop cs argument for recording traces
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16605 >
2022-05-19 19:04:28 +00:00
12773d4070
docs/u_trace: document u_trace usage
...
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16579 >
2022-05-19 17:57:36 +00:00
8cabf134a8
svga: fix aa point
...
Use in_prim from current geometry shader to check for point prim type
when determine if aa point is enabled or not.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16598 >
2022-05-19 17:17:12 +00:00
8cbcdb4f10
svga: add need_texcoord_semantic to tgsi_add_point_sprite & tgsi_add_aa_point
...
Since PIPE_CAP_TGSI_TEXCOORD is now set in SVGA vgpu10 driver,
we need to add a new parameter need_texcoord_semantic to
tgsi_add_point_sprite and tgsi_add_aa_point
to allow setting texcoords using tgsi texcoord semantic.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16598 >
2022-05-19 17:17:12 +00:00
5398c9183e
intel/ds: fix compilation
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6518
Fixes: efc2782f97https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16601 >
2022-05-19 16:42:41 +00:00
9565ea5640
docs: Add calendar entries for 22.1 release.
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610 >
2022-05-19 16:37:15 +00:00
35e3aea0b2
relnotes: Add sha256sum and fix minor formatting issues
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610 >
2022-05-19 16:37:15 +00:00
5944b9ab83
docs: add release notes for 22.1.0
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610 >
2022-05-19 16:37:15 +00:00
e84de9c04f
docs: update calendar and link releases notes for 22.1.0
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610 >
2022-05-19 16:37:15 +00:00
d6ece34d0c
pan/va: Use ^ instead of ` to indicate last-use
...
This syncs the ISA syntax with other Valhall ISA users. It's also somewhat
easier to read.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
9fb8ca1851
pan/va: Remove DISCARD.f32 destination
...
It doesn't actually write anything. This is a pointless divergence from Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
444469d64e
pan/va: Handle 2-src blend in lower_split_src
...
Fixes assertion fail in shaders/dolphin/smg.1.shader_test
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
0576cad958
pan/bi: Validate vector widths
...
Now that our IR is much more strongly typed, and RA code quality depends on
correct typing, add a validation pass to make sure we didn't screw it up. This
pass found a massive number of bugs in early versions of this series.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
Mike Blumenkrantz
Samuel Pitoiset
Iago Toral Quiroga
Hyunjun Ko
Lucas Stach
Sil Vilerino
Pierre-Eric Pelloux-Prayer
Hans-Kristian Arntzen
Jason Ekstrand
Qiang Yu
Nicolas Caramelli
Dylan Baker
Kenneth Graunke
Emma Anholt
Lionel Landwerlin
Danylo Piliaiev
Charmaine Lee
Alyssa Rosenzweig