Commit Graph

18425 Commits

Author SHA1 Message Date
José Fonseca 5aaa4bafe0 gallivm: Add and use lp_build_lerp_3d.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-05-17 20:22:50 +01:00
Tom Stellard e230d9debb radeon/llvm: Run standard optimization passes on conpute shader modules
The SROA and function inliner passes are espically important, because
they optimize away unsupported features: functions and indirect
private memory access.
2013-05-17 07:38:01 -07:00
Niels Ole Salscheider 7e17e72cb7 r600g: fixup for MSAA texture support checking
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
2013-05-16 12:03:47 -07:00
José Fonseca 4f518e1738 llvmpipe: Temporary workaround to prevent segfault on array textures. 2013-05-16 15:14:10 +01:00
José Fonseca cb9913cdab gallivm: Support pointers in lp_build_print_value().
Trivial.
2013-05-16 15:14:10 +01:00
Chia-I Wu 435aea6f32 ilo: emit 3DSTATE_STENCIL_BUFFER on GEN7+
Whether HiZ is enalbed or not, separate stencil is supported and enforced on
GEN7+.  Now that we support separate stencil resources, we know how to emit
3DSTATE_STENCIL_BUFFER.
2013-05-16 18:33:59 +08:00
Chia-I Wu 6b894e6900 ilo: add support for stencil resources on GEN7+
For allocations, we need to support stencil-only and separate stencil
resources.  For mapping, we need to support software tiling and
packing/unpacking for separate stencil resources.
2013-05-16 18:20:17 +08:00
Chia-I Wu 5c9b69d259 winsys/intel: test for and expose address swizzling
Without knowing whether addresses are swizzled or not, we cannot manipulate a
tiled surface in CPU.
2013-05-16 11:24:59 +08:00
Marek Olšák 5a3fac4d26 r600g: cleanup MSAA texture support checking
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-15 20:20:32 +02:00
Marek Olšák 61c995bc47 r600g: rewrite FMASK allocation, fix FMASK texturing with 2 and 4 samples
This fixes and enables texturing with compressed MSAA colorbuffers
on Evergreen and Cayman. For the first time, multisample textures work
on Cayman.

This requires the libdrm flag RADEON_SURF_FMASK.

v2: require libdrm_radeon 2.4.45

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-15 20:19:45 +02:00
José Fonseca 2a43dfda95 draw: More defensive coding in DRAW_GET_IDX.
Doesn't make a difference ATM, but just in case.
2013-05-15 16:59:28 +01:00
José Fonseca 1883e1d3e9 draw: Fix vsplit regression when the ib can be used directly.
`ib` no longer is offseted by `istart`.

Trivial.
2013-05-15 16:57:44 +01:00
Chia-I Wu c68424bac4 ilo: clean up transfer format conversion
Map the bo directly, instead of calling transfer_map().
2013-05-15 15:21:50 +08:00
Chia-I Wu cb57da421a ilo: rework transfer mapping method choosing
Always check if a bo is busy in choose_transfer_method() since we always need
to map it in either map() or unmap().  Also determine how a bo is mapped in
choose_transfer_method().
2013-05-15 15:21:50 +08:00
Chia-I Wu b6c307744f ilo: refactor transfer mapping
Add tex_get_box_offset() to compute transfer offet from the pipe_box.  Add
tex_get_slice_stride() to compute slice stride for a transfer.
2013-05-15 15:21:50 +08:00
Chia-I Wu 5af8641ce0 ilo: no writeback without PIPE_TRANSFER_WRITE
We should not write staging data back when PIPE_TRANSFER_WRITE is not set.
2013-05-15 15:08:54 +08:00
Chia-I Wu 46bb33bc21 ilo: minor cleanups for transfers
Rename some functions and reorder some code.
2013-05-15 15:08:54 +08:00
Chia-I Wu ca349e0217 ilo: simplify ilo_texture_get_slice_offset()
Always return a tile-aligned offset.  Also fix for W tiling.
2013-05-15 15:08:54 +08:00
Zack Rusin 013424678e draw/gs: fix extracting of the clip
The indices are not consecutive when using the geometry shader,
which means we were extracting non existing values. Create
an array of linear indices and always use it instead of the passed
indices. Found by Jose.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-05-14 04:04:08 -04:00
Zack Rusin 5104ed3dbf draw: try to prevent overflows on index buffers
Pass in the size of the index buffer, when available, and use it
to handle out of bounds conditions. The behavior in the case of
an overflow needs to be the same as with other overflows in the
vertex processing pipeline meaning that a vertex should still
be generated but all attributes in it set to zero.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-05-14 03:10:56 -04:00
Zack Rusin d5250da818 draw: use the total number of vertices for statistics
the number of vertices to fetch doesn't necessarily equal the
total number of input vertices, e.g. we might want to fetch
a single vertex but then draw it twice. Lets use the correct
number of input vertices in the statistics.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-05-14 03:10:33 -04:00
Zack Rusin 29853ab7b8 draw: don't crash on vertex buffer overflow
We would crash when stride was bigger than the size of the buffer.
The correct behavior is to just fetch zero's in this case.
Unfortunatly with user_buffer's there's no way to validate the size
because currently we're just not getting it. Adjust the draw interface
to pass the size along the mapped buffer, which works perfectly
for buffer backed vertex_buffers and, in future, it will allow
us to plumb user_buffer sizes through the same interface.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-05-14 03:09:32 -04:00
Zack Rusin 386327c48f gallivm/soa: implement indirect addressing in immediates
The support is analogous to the way we handle indirect addressing
in temporaries, except that we don't have to worry about storing
(after declarations) and thus we'll able to keep using the old
code when indirect addressing isn't used. In other words we're
still using constants directly, unless the instruction has
immediate register with indirect addressing.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-05-14 03:09:15 -04:00
Zack Rusin 2866525b86 draw/gs: don't bind the tgsi state if we're using llvm paths
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-05-14 03:08:56 -04:00
Vinson Lee ff256ec068 gallivm: Fix build with LLVM >= 3.4 r181680.
Tested-by: Laurent Carlier <lordheavym@gmail.com>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
2013-05-14 09:06:14 -07:00
Alex Deucher d188f14941 radeonsi: update r600_get_llvm_processor_name for hainan
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-05-14 10:51:10 -04:00
Alex Deucher 4045c3d060 radeonsi: add support for hainan chips
Note: this is a candidate for the 9.1 branch

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-05-14 10:51:10 -04:00
José Fonseca c475ae5d3d draw: Fix io_ptr/num_prims name in IR.
Trivial.
2013-05-14 15:36:37 +01:00
José Fonseca 2f3d939e36 graw/tgsi_dump: Fix gdb macro.
The macro was relying on "tokens" local variable to exist.
2013-05-14 15:36:37 +01:00
Vadim Girlin 560ddad261 r600g/sb: add missing cases for ARUBA chips
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-14 17:36:25 +04:00
Vadim Girlin ecde4b07e2 r600g/sb: get rid of standard c++ streams
Static initialization of internal libstdc++ data related to iostream
causes segfaults with some apps.

This patch replaces all uses of std::ostream and std::ostringstream in sb
with custom lightweight classes.

Prevents segfaults with ut2004demo and probably some other old apps.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-14 17:36:25 +04:00
Vadim Girlin 57d1be0d2d r600g/sb: separate bytecode decoding and parsing
Parsing and ir construction is required for optimization only,
it's unnecessary if we only need to print shader dump.
This should make new disassembler more tolerant to any new
features in the bytecode.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-14 17:36:25 +04:00
Christian König e195d301ae vl/vdpau: fix PresentationQueueQuerySurfaceStatus
The last queued surface always keeps displaying.

Fixing a problem with XBMC.

Signed-off-by: Christian König <christian.koenig@amd.com>
2013-05-14 15:16:15 +02:00
Chia-I Wu 176ad54c04 ilo: rework ilo_texture
Use ilo_buffer for buffer resources and ilo_texture for texture resources.  A
major cleanup is necessitated by the separation.
2013-05-14 16:07:22 +08:00
Chia-I Wu 768296dd05 ilo: rename ilo_resource to ilo_texture
In preparation for the introduction of ilo_buffer.
2013-05-14 16:01:25 +08:00
Chia-I Wu 528ac68f7a ilo: move transfer-related functions to a new file
Resource mapping is distinct from resource allocation, and is going to get
more and more complex.  Move the related functions to a new file to make the
separation clear.
2013-05-14 16:01:20 +08:00
Marek Olšák 52cb395bb1 gallium: add PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE for GL
v2: fix typo 65535 -> 65536

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-05-11 23:45:01 +02:00
Vinson Lee 5471e3949c ilo: Initialize read_back in transfer_map_sys.
Fixes "Uninitialized scalar variable" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2013-05-10 15:29:40 +08:00
Marek Olšák da33f9b919 r600g: increase array size for shader inputs and outputs
and add assertions to prevent buffer overflow. This fixes corruption
of the r600_shader struct.

NOTE: This is a candidate for the stable branches.
2013-05-10 03:23:31 +02:00
Chí-Thanh Christopher Nguyễn 121c2c8983 targets/dri-i915: Force c++ linker in all cases
NOTE: This is a candidate for the 9.1 branch.
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=461696
Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>
2013-05-09 17:04:27 -07:00
Courtney Goeltzenleuchter daa90f91ff ilo: Add support for HW primitive restart.
Now tells Gallium that ilo supports primitive restart.
Updated ilo_draw_vbo to be able to check that the indexed
primitive being rendered can actually be supported in HW. If not,
will break up into individual prims similar to what Mesa does.

[olv: a minor fix after rebasing and formatting]
2013-05-10 00:06:14 +08:00
Brian Paul 009d79734f svga: misc whitespace and comment fixes in svga_cmd.c 2013-05-09 07:43:46 -06:00
Chia-I Wu a8e4614071 ilo: add support for PIPE_FORMAT_ETC1_RGB8
It is decompressed to and stored as PIPE_FORMAT_R8G8B8X8_UNORM on-the-fly.
2013-05-09 16:05:48 +08:00
Chia-I Wu 183ea823fd ilo: support mapping with a staging system buffer
It can be used for unpacking compressed texture on-the-fly or to support
explicit transfer flushing.
2013-05-09 16:05:47 +08:00
Chia-I Wu baa44db065 ilo: allow for different mapping methods
We want to or need to use a different mapping method when when the resource is
busy, the bo format differs from the requested format, and etc.
2013-05-09 16:05:47 +08:00
Chia-I Wu 7cca1aac9d ilo: allow bo format to differ from that requested
For separate stencil buffer or formats not supported natively, the real format
of the bo may differ from that requested.
2013-05-09 16:05:47 +08:00
Stéphane Marchesin 1c56fc1025 draw/llvm: Add additional llvm optimization passes
It helps a bit with vertex shader performance on i915g
(a couple percent faster with openarena).

I have tried most other passes, and they weren't showing
any measurable improvement. Note that my vertex shaders
didn't have loops, so maybe the loop optimizations could
still be useful in the future.

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-05-08 22:05:54 -07:00
Stéphane Marchesin 38d2a16c01 i915: Use Y tiling for textures
This basically reverts commit
2acc719374.

With the previous change, we're not batchbuffer limited any
longer. So we actually start seeing a performance difference
between X and Y tiling. X tiling is funny because it is
faster for screen-aligned quads but slower in games. So let's
use Y tiling which is 10% faster overall.
2013-05-08 02:07:00 -07:00
Stéphane Marchesin fc24c7aede i915g: Optimize batchbuffer sizes
Now that we don't throttle at every batchbuffer, we can shrink
the size of batchbuffers to achieve early flushing. This gives
a significant speed boost in a lot of games (on the order of
20%).
2013-05-08 02:06:56 -07:00
Stéphane Marchesin 7f7c7fda83 i915g: Add more PIPE_CAP_* support 2013-05-08 01:37:55 -07:00