Commit Graph

22438 Commits

Author SHA1 Message Date
Marek Olšák 4fd8d2df9c radeonsi: move emission of PA_SU_VTX_CNTL into emit_guardband
We'll modify the quant mode there, which also affects the guarband
computation.
2018-10-16 15:28:22 -04:00
Marek Olšák 41a6c3de1f radeonsi: don't re-upload the sample position constant buffer repeatedly 2018-10-16 15:28:22 -04:00
Marek Olšák b94824c787 radeonsi: set PA_SU_PRIM_FILTER_CNTL optimally 2018-10-16 15:28:22 -04:00
Marek Olšák 9e182b8313 radeonsi: center viewport to improve guardband clipping for high resolutions
This will be more useful when we change the quant mode to increase subpixel
precision and decrease the viewport range (which might not be possible
if the viewport is not centered in the viewport range).
2018-10-16 15:28:22 -04:00
Marek Olšák fedc1fda30 radeonsi: save raster config in screen, add se_tile_repeat 2018-10-16 15:28:22 -04:00
Marek Olšák ac76aeef20 radeonsi: switch back to standard DX sample positions
Apps may rely on them.
2018-10-16 15:28:22 -04:00
Marek Olšák 67f02cf810 radeonsi: add GDS support to CP DMA 2018-10-16 15:28:22 -04:00
Marek Olšák 0d05581578 radeonsi: rename si_gfx_* functions to si_cp_*
and write_event_eop -> release_mem
2018-10-16 15:28:22 -04:00
Marek Olšák 6e1cf6532d radeonsi: make si_gfx_write_event_eop more configurable 2018-10-16 15:28:22 -04:00
Caio Marcelo de Oliveira Filho c20dd1f77c intel/nir, freedreno/ir3: Use the separated dead write vars pass
No changes to shader-db for intel.
No changes to shader-db expected for freedreno.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-10-15 17:29:46 -07:00
Eric Anholt 8ec83dc51e v3d: Add support for hardware pack/unpack of half floats.
Cuts the formerly 7-minute simulation time of fs-packHalf2x16.shader_test
in half.
2018-10-15 17:16:44 -07:00
Eric Anholt dda1ae9b3c gallium/ttn: Convert inputs and outputs to derefs of variables.
This means that TTN shaders more closely resemble GTN shaders: they have
inputs and outputs as variable derefs, with the variables having their
.driver_location already set up for you.

This will be useful for v3d to do input variable DCE in NIR, which we
can't do when the TTN shaders never have a pre-nir_lower_io stage.

Acked-by: Rob Clark <robdclark@gmail.com>
2018-10-15 17:16:43 -07:00
Kristian H. Kristensen f93e431272 freedreno/a6xx: Enable blitter
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2018-10-15 15:22:38 -07:00
Kristian H. Kristensen 47bc9fad3e freedreno/a6xx: Update headers
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2018-10-15 15:22:35 -07:00
Kristian H. Kristensen 421863412c freedreno/a6xx: Remove unnecessary GRAS_2D_BLIT_INFO write
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2018-10-15 15:20:28 -07:00
Kenneth Graunke 38a23517fd gallium/u_transfer_helper: Add support for separate Z24/S8 as well.
u_transfer_helper already had code to handle treating packed Z32_S8
as separate Z32_FLOAT and S8_UINT resources, since some drivers can't
handle that interleaved format natively.

Other hardware needs depth and stencil as separate resources for all
formats.  For example, V3D3 needs this for 24-bit depth as well.

This patch adds a new flag to lower all depth/stencils formats, and
implements support for Z24_UNORM_S8_UINT.  (S8_UINT_Z24_UNORM is left
as an exercise to the reader, preferably someone who has access to a
machine that uses that format.)

Reviewed-by: Eric Anholt <eric@anholt.net>
2018-10-14 23:36:28 -07:00
Vinson Lee cc33621e3b r600/sb: Fix constant-logical-operand warning.
sb/sb_bc_parser.cpp:620:27: warning: use of logical '&&' with constant operand [-Wconstant-logical-operand]
        if (cf->bc.op_ptr->flags && FF_GDS)
                                 ^  ~~~~~~
sb/sb_bc_parser.cpp:620:27: note: use '&' for a bitwise operation
        if (cf->bc.op_ptr->flags && FF_GDS)
                                 ^~
                                 &
sb/sb_bc_parser.cpp:620:27: note: remove constant to silence this warning
        if (cf->bc.op_ptr->flags && FF_GDS)
                                ~^~~~~~~~~

Fixes: da977ad907 ("r600/sb: start adding GDS support")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-10-12 10:58:58 -07:00
Brian Paul 797e34f658 svga: change svga_destroy_shader_variant() to return void
svga_destroy_shader_variant() itself flushes and retries the command
if there's a failure.  So no need for the callers to do it.  Other
callers of the function were already ignoring the return value.

This also fixes a corner-case double-free reported by Coverity
(and reported by Dave Airlie).

Tested with various OpenGL apps.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2018-10-09 11:17:14 -06:00
Ilia Mirkin 92f56fbd89 nvc0: fix blitting red to srgb8_alpha
For some reason the 2d engine can't handle this. Red formats get special
treatment there, so perhaps related.

Fixes dEQP-GLES3 tests of the form:

  dEQP-GLES3.functional.fbo.blit.conversion.r{8,16f,32f}_to_srgb8_alpha8

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
2018-10-09 10:33:11 -04:00
Ilia Mirkin 9bf0614116 nv50,nvc0: guard against zero-size blits
The current state tracker can generate these sometimes. Fixing this is
more involved, and due to some integer math we can generate
divisions-by-zero.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
2018-10-09 10:33:11 -04:00
Ilia Mirkin 78d3640e49 nv50,nvc0: mark RGBX_UINT formats as renderable
This helps st/mesa avoid some (apparently) buggy fallbacks. Specifically
the CopyTexSubImage fallback tries to read texture A as RGBA_FLOAT and
write back that data into the target format, which fails for integer
formats which have no appropriate logic to do the conversion.

Since integer formats don't blend, there's no harm in the fact that the
"A" component gets written anyways.

Fixes, among others:
  https://www.khronos.org/registry/webgl/sdk/tests/conformance2/textures/canvas/tex-2d-rgb8ui-rgb_integer-unsigned_byte.html

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2018-10-09 10:33:11 -04:00
Rob Clark fa52ff856d freedreno/a5xx+a6xx: fix LRZ pitch alignment
Both RB_2D_DST_SIZE.PITCH (a6xx) and RB_MRT[n].PITCH (a5xx) need
alignment to 64.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 19:05:14 -04:00
Rob Clark 82c3b6fe49 freedreno/a6xx: add LRZ support
As with a5xx, hidden behind FD_MESA_DEBUG=lrz due to being paranoid
about z-fighting issues with some games (in particular, this was
observed with 0ad on a5xx.. but I think the proper solution to enable
this by default is to figure out how to do driver specific driconf
options).

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 19:05:14 -04:00
Rob Clark a877451a41 freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 18:03:35 -04:00
Rob Clark bf79a7cc25 freedreno/a6xx: add helper for various CP_EVENT_WRITE
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 17:50:26 -04:00
Rob Clark 60af89815e freedreno/a6xx: remove unused fxns
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 17:50:26 -04:00
Rob Clark d5bd3ce89c freedreno/a6xx: remove fd6_shader_stateobj
Earlier gen's already got this cleanup, but a6xx was still off on a
branch then.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 17:50:26 -04:00
Marek Olšák d877451b48 util/u_queue: add UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
Initial version discussed with Rob Clark under a different patch name.
This approach leaves his driver unaffected.
2018-10-06 22:05:58 -04:00
Marek Olšák 066aa44fc5 radeonsi: fix a typo at CS_PARTIAL_FLUSH
harmless
2018-10-06 21:50:52 -04:00
Marek Olšák 77903c8cfb ac: add ac_build_round 2018-10-06 21:50:09 -04:00
Marek Olšák fa023f293e ac: correct PKT3_COPY_DATA definitions 2018-10-06 21:50:09 -04:00
Marek Olšák a668c8d6ba ac: define all address spaces properly 2018-10-06 21:50:09 -04:00
Sonny Jiang 084cf3b966 radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuse
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang ce1d72609d radeonsi:optimizing SET_CONTEXT_REG for shaders Tessellation
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang 4de328da07 radeonsi:optimizing SET_CONTEXT_REG for shaders PS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang f243980f2c radeonsi:optimizing SET_CONTEXT_REG for shaders VS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang 4052624398 radeonsi:optimizing SET_CONTEXT_REG for shaders GS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Marek Olšák 86f004bdfc radeonsi: optimize and allow reg > 31 in radeon_opt_set_context_reg functions
reg_saved will have 64 bits, and (1 << reg) where reg > 31 has undefined
behavior. (1ull << reg) would be correct for 64 bits.

This commit shifts the other way in order to merge the conditions.
2018-10-05 19:04:13 -04:00
Sonny Jiang eeb9170599 radeonsi: optimizing SET_CONTEXT_REG for shaders ES
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 17:53:52 -04:00
Guido Günther b2a876a42b etnaviv: Use write combine instead of unached mappings for shader bo
The later are sensitive to unaligned accesses on arm64[1] and we don't
need an uncached mapping here.

[1]: https://lists.freedesktop.org/archives/etnaviv/2018-September/001956.html

Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2018-10-04 10:33:25 +02:00
Emil Velikov c231b49c53 freedreno: add the a6xx sources to the Android build
Add the files otherwise things just won't build.
Haven't actually tested it, but it's a small step in the right
direction.

Fixes: de3b34df97 ("freedreno: Add a6xx backend")
Cc: Kristian H. Kristensen <hoegsberg@chromium.org>
Cc: Rob Clark <robdclark@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2018-10-03 13:38:05 +01:00
Timothy Arceri 2b5f42068d r600: use build-id when available for disk cache
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-03 09:49:21 +10:00
Timothy Arceri 397f2603eb nouveau: use build-id when available for disk cache
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-03 09:49:21 +10:00
Timothy Arceri 2169acbf34 radeonsi: use build-id when available for disk cache
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-03 09:49:21 +10:00
Józef Kucia e24a4e05c7 radeonsi: avoid sending GS_EMIT in shaders without outputs
Fixes GPU hangs.

Cc: 18.1 18.2 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107857
Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-02 17:13:52 -04:00
Marek Olšák 2fd58d8eb2 radeonsi: initialize ac_gpu_info::name when using SI_FORCE_FAMILY
so that it's not NULL when loading radeonsi and a GCN GPU is not
present in the system.
2018-10-02 12:21:49 -04:00
Marek Olšák 0b062f0419 radeonsi: don't set the VS prolog key for the blit VS 2018-10-02 12:21:49 -04:00
Rob Clark ae78489d3e freedreno/a6xx: hwbinning
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-02 10:08:18 -04:00
Rob Clark 8ff349e564 freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-02 10:08:18 -04:00
Timothy Arceri 0e6cdfd561 radeonsi: add a workaround for bitfield_extract when count is 0
This ports the fix from 3d41757788. Both LLVM 7 & 8 continue
to have this problem.

It fixes rendering issues in some menu and loading screens of
Civ VI which can be seen in the trace from bug 104602.

Note: This does not fix the black triangles on Vega for bug
104602.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107276
2018-10-02 08:39:51 +10:00