Commit Graph

146710 Commits

Author SHA1 Message Date
Boyuan Zhang 4abc6d64e7 radeon/vcn: update vcn2 enc interface
Add missing parameters according to vcn 2 encode interface.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
2021-10-28 23:44:14 +00:00
Boyuan Zhang 299097d17b radeon/vcn: update vcn1 enc interface
Update vcn 1 encode interface, upgrade interface minor version from 2 to 9,
and add necessary parameters accordingly.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
2021-10-28 23:44:14 +00:00
Emma Anholt 8fb850651c ci: Enable testing radeonsi's libva using libva-util unit tests.
We've noticed issues with these tests when uprevving Mesa in Chrome OS.
This CI catches some existing failures, and some debug-build assertion
failures as well.

To do this, uprev deqp-runner for its new gtest-runner command.  This
runner is not as efficient as I would hope, due to some expensive code in
gtest.  I've reported the issue to gtest and it should be easily fixable,
but for now it at least means we get to use the same baseline/skip/flake
handling we have from deqp and piglit runners.

I also fixed build-libdrm for our rootfses to not throw away libdrm's
share directory, which was causing a bunch of test-time spam from radeon's
libdrm when trying to look up its marketing name tables (not that big of a
deal for deqp-runner, but really noisy for piglit and libva-utils which
make gallium screens approximatly per-test).

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13419>
2021-10-28 23:17:19 +00:00
Connor Abbott e6ae0e9b95 freedreno/a6xx: Emit GRAS_LRZ_MRT_BUF_INFO_0
Analogous to the previous commit, this fixes the case where turnip sets
this reg to a media (yuv) format and then a gallium job is run next.

Fixes: 9c895e13 ("tu: Emit GRAS_LRZ_MRT_BUF_INFO_0")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13578>
2021-10-28 22:19:09 +00:00
Connor Abbott 98c1448509 tu: Always write GRAS_LRZ_MRT_BUF_INFO_0
This fixes flakes in dEQP-VK.pipeline.stencil.nocolor.format.* when run
after ycbcr tests. Apparently LRZ needs to know if there's a media
format enabled even if there are no color attachments, so we need to
write something here. Presumably any "normal" format would work but 0
seems like a good neutral choice.

Fixes: 9c895e13 ("tu: Emit GRAS_LRZ_MRT_BUF_INFO_0")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13578>
2021-10-28 22:19:09 +00:00
Kenneth Graunke 2f58a63b2f intel/genxml: Add XY_BLOCK_COPY_BLT on Tigerlake and later.
This is a new blitter command introduced on Tigerlake and expanded
substantially on XeHP.  XY_BLOCK_COPY_BLT is actually fast, unlike
the legacy blitter commands.  iris will use this in the future, and
anv hopefully could use it for a transfer queue someday as well.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520>
2021-10-28 14:17:32 -07:00
Kenneth Graunke 9163500aa1 intel/genxml: Allow MI_FLUSH_DW on the blitter
Pretty sure this is how you flush the blitter.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520>
2021-10-28 14:17:32 -07:00
Kenneth Graunke d9ffdfc16d intel/genxml: Include blitter commands in gen*_pack.h
We're going to want to use the blitter again on newer hardware,
which means we need to be able to use genxml to emit those commands.

Acked-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520>
2021-10-28 14:17:29 -07:00
Kenneth Graunke 7b78b2fcac intel/genxml: Assert that all MOCS fields are non-zero on Gfx7+
Let's try and catch performance problems before we have to do large
painful amounts of analysis to detect a missed field.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke ebe2a2b5f6 intel/genxml: Add an field option for nonzero="true"
This asserts that the value supplied is non-zero.  Useful for things
like MOCS fields on modern platforms where we really want to avoid
setting it to 0 (uncached).

mbz types cannot be flagged as nonzero.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke e6ebf5add7 i965: Set MOCS for Bindless Surface/Sampler State base addresses
We don't use bindless surface or sampler states today, and are unlikely
to ever implement that in i965, but we can set a MOCS value regardless
to avoid asserts in upcoming patches that assert MOCS isn't zero.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke 148ea65ee1 i965: Port STATE_BASE_ADDRESS to genxml and fix bugs
This largely copies crocus's code for this (but with Gfx9+ handling).

This version also fixes missing MOCS settings on several platforms,
which we hadn't noticed were missing.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke 0a64007676 i965: Fix MOCS for BLORP buffer copies
We were passing a MOCS of 0, which is uncached.  Yikes.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke 75e86afb50 i965: Set MOCS for 3DSTATE_INDEX_BUFFER on Gfx6/7 as well.
For some reason we were only setting this on Gfx8+.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke ab44a54646 i965: Set MOCS for 3DSTATE_SO_BUFFERS on Gfx7.x too
For some reason we were only setting this on Gfx8+.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke eaaa3c7e04 i965: Set MOCS on NULL stream output buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is disabled stream output targets,  MOCS shouldn't matter, as
there's no actual buffer to be cached.

That said, it should be harmless to set MOCS for these null stream
output buffers; we can just assume a MOCS for generic internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke 59f53b07c4 i965: Set MOCS for push constant buffers on Haswell and Gfx9+
We set MOCS on Ivybridge/Baytrail, but not Haswell, and not Skylake
and later.  We shoud set it everywhere.  While we're at it, we also
set it for null constant buffers, so that we aren't programming a 0
MOCS, to allow us to add some safeguards against that.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke d0e356b333 i965: Set default MOCS for NULL depth/stencil/HiZ buffers
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero.  When we have entirely NULL surfaces, we just
default to the MOCS value for an internal buffer.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke f0a5f10b6c i965: Use ISL for MOCS rather than open coding it everywhere
The ISL MOCS infrastructure didn't exist when we wrote the i965 code,
but now that it does, we ought to use it, deleting a complicated mess
that was replicated all throughout the codebase.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke d9decdb2c4 crocus: Fix MOCS for buffer copies.
We were passing a MOCS of 0, which is uncached.  Yikes.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke dc29e9dbb3 crocus: Set MOCS for 3DSTATE_SO_BUFFERS on Gfx7.x too
For some reason we were only setting this on Gfx8+.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 72ffcd1965 crocus: Set MOCS for push constant buffers where possible
We apparently were not setting MOCS for 3DSTATE_CONSTANT_XS at all.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 798cc4be1b crocus: Set default MOCS for NULL depth/stencil/HiZ buffers
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero.  When we have entirely NULL surfaces, we just
default to the MOCS value for an internal buffer.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 737b3fae73 crocus: Set MOCS on NULL stream output buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is disabled stream output targets,  MOCS shouldn't matter, as
there's no actual buffer to be cached.

That said, it should be harmless to set MOCS for these null stream
output buffers; we can just assume a MOCS for generic internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke de99b5502b crocus: Set MOCS for index buffers on Gen6+
For some reason we were only setting them on Gen8+.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke be0d22a9ce crocus: Tidy the ifdefs for emitting STATE_BASE_ADDRESS
This reorganizes the code so that we set fields in a tidy order:

   1. Set the base addresses

   2. Set either buffer sizes (Gfx8) or upper bound values (Gfx4-7)
      (These are logically the same thing, but expressed differently.)

   3. Set MOCS (Gfx6+)

I find this easier to follow.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 51f843ad60 crocus: Set MOCS for most state base addresses on pre-Gen8
We were only setting MOCS for dynamic state, surface state, instruction,
and indirect base addresses on Gen8+.  We should set them on Gen6+.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke dfe455b6df anv: Set MOCS on NULL stream output buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is disabled stream output targets,  MOCS shouldn't matter, as
there's no actual buffer to be cached.

That said, it should be harmless to set MOCS for these null stream
output buffers; we can just assume a MOCS for generic internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 818b5d2b9e anv: Set MOCS on NULL vertex buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is 3DSTATE_VERTEX_BUFFERS where we set NullVertexBuffer.
It shouldn't matter here, as there's no actual buffer to be cached.

That said, it should be harmless to set MOCS for null vertex buffers.
We can assume an internal buffer and request isl's vertex buffer MOCS.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 7ae9f516f0 anv: Set MOCS in 3DSTATE_CONSTANT_XS even if there isn't a buffer.
This avoids MOCS != 0 assertions in later patches.  iris also does this,
and we do it for the 3DSTATE_CONSTANT_ALL packet path as well.  It's a
bit pointless, but it should hopefully be harmless also.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 158ad07b3e anv: Set MOCS for 3DSTATE_CONSTANT_XS on Gfx7.x as well
We were only setting this on Gfx9+.  It's MBZ on Gfx8, but it exists
on Gfx7.x and doesn't have those restrictions there; we should set it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke b4310ef8ee anv: Set default MOCS for NULL depth/stencil/HiZ buffers
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero.  When we have entirely NULL surfaces, we just
default to isl's MOCS value for an internal depth buffer.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke d8cb76211c iris: Fix MOCS for buffer copies
We were passing a MOCS of 0, which is uncached.  Yikes.

Fixes: c5b22441f1 ("iris: Fix buffer -> buffer copy_region")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 256d48eb8c iris: Set MOCS on NULL stream output buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is disabled stream output targets,  MOCS shouldn't matter, as
there's no actual buffer to be cached.

That said, it should be harmless to set MOCS for these null stream
output buffers; we can just assume a MOCS for generic internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke d8e1d0fecc iris: Set MOCS on NULL vertex buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is 3DSTATE_VERTEX_BUFFERS where we set NullVertexBuffer.
It shouldn't matter here, as there's no actual buffer to be cached.

That said, it should be harmless to set MOCS for null vertex buffers.
We can assume an internal buffer and request isl's vertex buffer MOCS.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 369cd9ae28 iris: Set MOCS on 3DSTATE_CONSTANT_ALL packets that disable all buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we missed
setting a non-zero MOCS was in 3DSTATE_CONSTANT_ALL packets which fully
disable all constant buffers.  (If any constant buffer was present, we
would set an actual MOCS value.)

MOCS really shouldn't matter here, as there are no actual constant
buffers to be cached.  That said, it should be harmless to do so, and
we can just assume a generic MOCS for internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 0544afd2df iris: Set MOCS on 3DSTATE_CONSTANT_XS on Gfx9+
We were leaving this blank due to a Broadwell restriction, causing our
constant buffers to be uncached.  We later fixed this for Gfx12+, but
left Gfx9-11 without a fix.  We should specify one.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 8336054024 iris: Set default MOCS for NULL depth/stencil/HiZ buffers
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero.  When we have entirely NULL surfaces, we just
default to isl's MOCS value for an internal depth buffer.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 0a5e225779 iris: Set Bindless Sampler State MOCS
We don't use bindless sampler states today, but when we do, we'll want
them to have proper MOCS values.  This also avoids asserts in upcoming
patches which enforce that MOCS isn't zero.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke a6690dc1ee iris: Drop unnecessary parenthesis
Trivial.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke fc5168b01d blorp: Use a non-zero MOCS for disabled constant buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is disabled constant buffers, where MOCS shouldn't matter, as
there's no actual buffer to be cached.

That said, it should be harmless to set MOCS for these null constant
buffers; we can just assume a generic MOCS for internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 28a503c1a1 blorp: Fill in MOCS for null depth/stencil/HiZ buffers.
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero.  We just assume a generic internal MOCS when we
have entirely NULL surfaces.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke edce4649b8 blorp: Fill in MOCS even for SURFTYPE_NULL surfaces.
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is SURFTYPE_NULL surfaces, where MOCS really shouldn't matter,
as there's no actual surface to be cached.

That said, it should be harmless to set MOCS for these null surfaces;
we can just assume a generic MOCS for internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke c27fcb1d3b isl: Fill in MOCS for NULL depth, stencil, and HiZ buffers.
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is SURFTYPE_NULL depth, stencil, and HiZ buffers, where MOCS
really shouldn't matter, as there's no actual surface to be cached.

That said, it should be harmless to set MOCS for these null surfaces.
We now set the one provided in info->mocs regardless of whether any
buffers actually exist or not.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 801ecb6f12 isl: Fill in MOCS even for SURFTYPE_NULL surfaces.
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is SURFTYPE_NULL surfaces, where MOCS really shouldn't matter,
as there's no actual surface to be cached.

That said, it should be harmless to set MOCS for these null surfaces;
we can just assume a generic MOCS for internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 78d2605e57 intel/genxml: Change 3DSTATE_CONSTANT_XS::MOCS to be MBZ on Gfx8.
The Broadwell PRM says: "Constant Buffer Object Control State must
always be programmed to zero."

This patch changes the MOCS field in gen8.xml to be "mbz" type, so that
it's impossible to set it to a non-zero value.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 956effb88a intel/genxml: Drop "Hierarchical Depth Buffer MOCS" field
This is redundant with the existing "MOCS" field.  We don't need both.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke e69d395cd1 intel/genxml: Add an "mbz" data type
There are some fields which Must Be Zero, and we don't want to allow
setting them from the template struct, but we do want them in the XML
to allow them to be decoded properly, and for documentation purposes.

This adds a new "mbz" type, much like "mbo", except it doesn't set
anything in the struct.  We also update the decoder to handle it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke 58dc7f6ea6 intel/genxml: Fix Indirect Object Access Upper Bound on Gfx4
We had this field mislabeled as "Instruction Access Upper Bound", but
instruction state base address doesn't exist until Gfx5.  This is
supposed to be the upper bound for indirect object base address,
matching the G45 copy.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Pierre-Eric Pelloux-Prayer cf76247f38 drirc: enable do_dce_before_clip_cull_analysis for ANSA
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12897>
2021-10-28 18:01:04 +00:00