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intel/genxml: Fix Indirect Object Access Upper Bound on Gfx4 

We had this field mislabeled as "Instruction Access Upper Bound", but
instruction state base address doesn't exist until Gfx5.  This is
supposed to be the upper bound for indirect object base address,
matching the G45 copy.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
This commit is contained in:
Kenneth Graunke 2021-10-22 02:33:04 -07:00 committed by Marge Bot
parent cf76247f38
commit 58dc7f6ea6
1 changed files with 2 additions and 2 deletions
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4
src/intel/genxml/gen4.xml
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@ -936,8 +936,8 @@
<field name="Indirect Object Base Address" start="108" end="127" type="address"/>
<field name="General State Access Upper Bound Modify Enable" start="128" end="128" type="bool"/>
<field name="General State Access Upper Bound" start="140" end="159" type="address"/>
<field name="Instruction Access Upper Bound Modify Enable" start="160" end="160" type="bool"/>
<field name="Instruction Access Upper Bound" start="172" end="191" type="address"/>
<field name="Indirect Object Access Upper Bound Modify Enable" start="160" end="160" type="bool"/>
<field name="Indirect Object Access Upper Bound" start="172" end="191" type="address"/>
</instruction>
<instruction name="STATE_SIP" bias="2" length="2" engine="render">