Commit Graph

135593 Commits

Author SHA1 Message Date
Marek Olšák d47c44add8 radeonsi: gather info about bindless images and memory stores with strstr(intr)
This is only code simplification.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9028>
2021-02-17 04:49:24 -05:00
Marek Olšák 5e47d6fc73 radeonsi: fix the value of uses_bindless_samplers
We don't have any nir_variables for uniforms, so this code wasn't
doing anything. Also, uniform handles are almost always uniforms.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9028>
2021-02-17 04:49:24 -05:00
Marek Olšák 19e6601413 radeonsi: do late NIR optimizations after uniform inlining
This was missing.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9028>
2021-02-17 04:49:24 -05:00
Marek Olšák 33ac9dec91 radeonsi: allocate filled_size for streamout targets in set_streamout_buffers
so that create_stream_output_target doesn't use the context and can be
called from any thread. This is for u_threaded_context.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9028>
2021-02-17 04:49:24 -05:00
Marek Olšák 9db4b331f9 radeonsi: improve comments in si_emit_derived_tess_state
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9028>
2021-02-17 04:49:24 -05:00
Marek Olšák 98ea523e00 radeonsi: for tess, determine the minimum num_patches before optimizing tg size
Doing these MINs at the end could have undone optimizations for the LDS
size and threadgroup size, so move the MINs up.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9028>
2021-02-17 04:49:24 -05:00
Marek Olšák 4fe37b850a ac/surface: use family_id so as not to crash with SI_FORCE_FAMILY in addrlib
We can't invoke gfx6 addrlib (overridden by SI_FORCE_FAMILY) with a gfx9
family ID.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9028>
2021-02-17 04:49:24 -05:00
Pierre-Eric Pelloux-Prayer a67d3e7c9e radeonsi: fix si_check_render_feedback
si_check_render_feedback only relied on si_images::enabled_mask and
si_samplers::enabled_mask to determine if a texture was being used
both as input and output.

Given that some samplers/images can be considered active (so accounted
for by enabled_mask) but not used by the current shader this could
lead to false-positive.

This commit fixes this by and-ing the above mask with the information
from shader_info for each active shader.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4227
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8869>
2021-02-17 09:11:46 +00:00
Pierre-Eric Pelloux-Prayer bddc0e023c radeonsi: fix read from compute / write from draw sync
A compute dispatch should see the result of a previous draw command.
radeonsi was missing this implicit sync, causing rendering artifacts:
the compute shader was reading from a texture still being written to
by the previous draw.

Framebuffer BOs are marked with RADEON_USAGE_NEEDS_IMPLICIT_SYNC,
so compute jobs will sync.

v2: use RADEON_USAGE_NEEDS_IMPLICIT_SYNC
v3: unconditionally make CB coherent after a flush

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com> (v3)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v3)
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4032
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2878
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1336
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8869>
2021-02-17 09:11:46 +00:00
Pierre-Eric Pelloux-Prayer a8373b3d38 radeonsi: store si_context::xxx_shader members in union
This allows to access them individually (sctx->shader.ps) or
using array indexing (sctx->shaders[PIPE_SHADER_FRAGMENT]).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8869>
2021-02-17 09:11:46 +00:00
Pierre-Eric Pelloux-Prayer 47ed009194 radeonsi: fix indentation issue in si_texture.c
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8869>
2021-02-17 09:11:46 +00:00
Iago Toral Quiroga 064b846949 broadcom/compiler: don't dump shader-db stats for failed shaders
Shaders that fail register allocation were dumped with an instruction
count of 0, so getting them to compile would show up as an instruction
count regression. Also, the LOST/GAINED stats depend on us not dumping
data for failed shaders, which is why we were always seeing 0/0 there.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9077>
2021-02-17 09:01:02 +01:00
Iago Toral Quiroga df6c19c1fd broadcom/compiler: use a helper function to decide on TMU spilling
As we add more compiler optimizations that can increase register pressure
we may decide to disallow TMU spilling in more cases so it is probably
better to move this to its own helper function.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9077>
2021-02-17 09:01:02 +01:00
Iago Toral Quiroga 14af7b3085 broadcom/compiler: don't emit redundant ldunif
If we emit a new uniform and that uniform has already been emitted
in the same block we can just reuse that.

There is a balancing game here between reducing ldunif instructions
and not increasing register pressure too much though, so we put
a limit to how far back we are willing to look for a previous
definition of the uniform. Based on shader-db results, 20 instructions
produces best results.

total instructions in shared programs: 14928266 -> 14907432 (-0.14%)
instructions in affected programs: 6431841 -> 6411007 (-0.32%)
helped: 15270
HURT: 10772
Instructions are helped.

total uniforms in shared programs: 3944672 -> 3840276 (-2.65%)
uniforms in affected programs: 1827184 -> 1722788 (-5.71%)
helped: 30423
HURT: 845
Uniforms are helped.

total inst-and-stalls in shared programs: 14957813 -> 14936873 (-0.14%)
inst-and-stalls in affected programs: 6475349 -> 6454409 (-0.32%)
helped: 15287
HURT: 10852
Inst-and-stalls are helped.

v2 (Eric):
 - consider ldunifrf too
 - check that no other instruction writes to the register

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9077>
2021-02-17 09:01:01 +01:00
Samuel Iglesias Gonsálvez 8dd54778fa turnip: VK_EXT_memory_budget implementation
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8524>
2021-02-17 08:07:33 +01:00
Samuel Iglesias Gonsálvez 4342dec09a turnip: keep track of memory heap usage, size and flags
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8524>
2021-02-17 08:07:19 +01:00
Samuel Iglesias Gonsálvez 182fb988c8 util: fix parsing of /proc/meminfo MemAvailable value
It was interpreting the value as hexadecimal when it is unsigned.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8524>
2021-02-17 08:06:15 +01:00
Vinson Lee a7a7d25e5b etnaviv: Fix memory leak in etna_vertex_elements_state_create.
Fix defect reported by Coverity Scan.

Resource leak (RESOURCE_LEAK)
leaked_storage: Variable cs going out of scope leaks the storage it points to.

Fixes: c9e8b49b88 ("etnaviv: gallium driver for Vivante GPUs")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9034>
2021-02-16 20:53:51 -08:00
Jason Ekstrand 3ce6ca7214 intel/fs: Shuffle can't handle source modifiers
On Gen7, we have to split shuffles into two MOVs for 64-bit types so we
can't handle source modifiers.  On Gen12.5, we have to use integer types
all the time so we can't use them there either.  Fixing that will be a
different commit but it interacts with this one.

Fixes: 90c9f29518 "i965/fs: Add support for nir_intrinsic_shuffle"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9068>
2021-02-17 03:59:25 +00:00
Jason Ekstrand 12fa219768 nir/opt_large_constants: Handle generic pointers
We already throw out any variables which may have a complex use so we
just need to make sure that our mode checks don't assert if we have a
deref which may_be but not must_be nir_var_function_temp.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9068>
2021-02-17 03:59:25 +00:00
Jason Ekstrand 8b133a1b25 nir: Fix parameter order in the bcsel-of-shuffle optimization
Fixes: 4ff4d4e569 "nir/opt_intrinsic: Optimize bcsel(b, shuffle..."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9068>
2021-02-17 03:59:25 +00:00
Jason Ekstrand ceb6986d34 nir: Don't optimize bcsel-of-shuffle across blocks
We can't move the shuffle to a new block so this only works if the
shuffle and the bcsel are in the same block.  Fortunately, in the
motivating case, this is true.

Also, we have to be careful around discard.  We could try really hard to
just avoid moving them past discard but we choose to simply bail if we
see a discard instead.

Fixes: 4ff4d4e569 "nir/opt_intrinsic: Optimize bcsel(b, shuffle..."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9068>
2021-02-17 03:59:25 +00:00
James Jones 129d83cac2 nouveau: Use format modifiers in buffer allocation
The nvc0 nouveau backend already claimed to support format modifiers, but
in practice it ignored them when allocating buffers outside of a
perfunctory check for the linear modifier in the first element of the
format modifier list.

This change deduces the supported modifiers, if any, for a given miptree
creation request, prioritizes them based on performance and memory waste
properties, compares the requested modifiers against the prioritized list
of supported modifiers, and overrides the internal layout calculations
based on the layout defined by the resulting modifier.

Additionally, if modifiers are provided and none are compatible with the
miptree creation request, the function now fails.  This brings the nouveau
behavior in line with other drivers such as i965 and etnaviv.

Signed-off-by: James Jones <jajones@nvidia.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3724>
2021-02-17 03:52:53 +00:00
James Jones df451091ac nouveau: no modifier != the invalid modifier
Other drivers fail resource allocation when a list of modifiers for the
resource is provided but none are supported. This includes cases when the
never-supported DRM_FORMAT_MOD_INVALID modifier is explicitly passed.  To
enable matching that functionality in nouveau, use an empty modifier list
rather than creating a one-entry list containing only
DRM_FORMAT_MOD_INVALID when the non-modifier resource creation function is
used.

This change stops short of failing allocations when no modifier is
specified, because the current code ignores all modifiers except the linear
modifier when creating resources, so there is not yet a framework in place
to determine which modifiers are valid for a given resource creation
request, and hence no way to reject only those which are invalid.

Signed-off-by: James Jones <jajones@nvidia.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3724>
2021-02-17 03:52:53 +00:00
James Jones cf999b3cc3 nouveau: Use DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D
Replace existing usage of the NVIDIA_16BX2_BLOCK format modifiers with
parameterized use of the more general macro.  Nouveau will now report
support for slightly different modifiers depending on whether the
underlying chip is a tegra GPU or not, and will potentially report valid
format modifiers for more resource types, but overall this should be a
functional no-op for existing applications.

Signed-off-by: James Jones <jajones@nvidia.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3724>
2021-02-17 03:52:53 +00:00
James Jones ff534e1b50 nouveau: Stash supported sector layout in screen
Older Tegra GPUs use a different sector bit swizzling layout than desktop
and Xavier GPUs. Hence their format modifiers must be differentiated from
those of other GPUs.  As a precursor to supporting more expressive block
linear format modifiers, deduce the sector layout used for a given GPU from
its chipset and stash the layout in the nouveau screen structure.

Signed-off-by: James Jones <jajones@nvidia.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3724>
2021-02-17 03:52:53 +00:00
Mike Blumenkrantz c4cc3d915b zink: add a disk cache for pipeline objects
this writes the pipeline cache to disk on shutdown

ideally we'd rather write this incrementally any time we make a new pipeline,
but that ends up breaking the disk cache infrastructure since we're always writing
to the same file, so this is the best we can do for now

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9094>
2021-02-17 02:59:52 +00:00
Mike Blumenkrantz eb3cb170fc zink: create a VkPipelineCache object on the screen and use it
this enables reuse of shaders across pipelines

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9094>
2021-02-17 02:59:52 +00:00
Mike Blumenkrantz de6ed18584 zink: hook up valid_buffer_range for buffer resources using util_range
this lets us avoid stalling during transfer map in some cases

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9062>
2021-02-17 02:16:59 +00:00
Mike Blumenkrantz 8b6e7d00f0 zink: add flag for no-oping fence finish
if a fence hasn't been activated then we don't need to wait on it

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9067>
2021-02-17 01:48:07 +00:00
Rob Clark 25a37c030b freedreno/ir3: Add missing shader prog cache invalidation
I'm not aware of actually hitting this case, but we need to consider
more than just vs/fs when shader state is deleted.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
2021-02-16 23:43:44 +00:00
Rob Clark 75b0c4b5e1 freedreno/ir3: Async shader compile
Draw-time variants are still synchronous, but I'm not sure there is much
(easy) benefit from generating them asynchronously.  Without patching
the cmdstream later before batch submit, we'd end up waiting for them
immediately.  But we should mostly only hit draw-time variants for
desktop GL (and mostly legacy features).

Note: new xfb xfail on a5xx, but most of the xfb tests are already xfail
so I think we just managed to change the timing a bit, rather than this
being related to async compile.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3857
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
2021-02-16 23:43:44 +00:00
Rob Clark 132512822b freedreno/ir3: Reshuffle compute state creation
There was just a single remaining caller of ir3_shader_create_compute(),
so fold that into ir3_shader_compute_state_create().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
2021-02-16 23:43:44 +00:00
Rob Clark f4ab72d8e8 freedreno/ir3: Reshuffle ir3_shader_create()
This had only a single caller, so no need to be exported.  With
that done, fold the ir3_shader creation (ie. the cheap part) into
ir3_shader_state_create(), and rename what is left.

This is prep to moving initial variant creation to a work queue.

It does slightly change the error handling, in that we don't
cleanup the shader hwcso.  We wouldn't be able to do this anyways
with async compile.  But it ends up using the same error handling
paths that we'd hit if we got a compile failure for a draw-time
variant.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
2021-02-16 23:43:44 +00:00
Rob Clark 7100bb1ebc freedreno/ir3: Add ir3_screen_fini()
Move ir3_compiler_destroy() into ir3_screen_fini().  This gives us a
good place to cleanup an sync compile queue.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
2021-02-16 23:43:43 +00:00
Rob Clark 90031adfc7 freedreno/ir3: Move ir3_compiler_create()
All the ir3 using backends already call ir3_screen_init(), so lets just
move compiler creation there.

In a subsequent patch, we'll add initialization of the queue for async
compile.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
2021-02-16 23:43:43 +00:00
Rob Clark 6fdd1d30f6 freedreno/ir3: Add ir3_shader_state
Initially just a wrapper for ir3_shader, but this is where we'll hook in
the bookkeeping for async compile.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
2021-02-16 23:43:43 +00:00
Rob Clark 378c14331b freedreno/ir3+a5xx+a6xx: De-duplicate create_compute_state()
These were identical between a5xx and a6xx, so move into shared helper
that can be directly plugged into pctx, similar to the various 3d shader
state creation.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
2021-02-16 23:43:43 +00:00
Rob Clark f673266191 freedreno/a6xx: Drop fd6_compute_stateobj
It wasn't really doing anything useful.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
2021-02-16 23:43:43 +00:00
Rob Clark d2bcbb6792 freedreno/a5xx: Drop fd5_compute_stateobj
It wasn't really doing anything useful.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
2021-02-16 23:43:43 +00:00
Rob Clark 6ed94905a6 freedreno: Misc cleanup
Some whitespace cleanup + comment addition.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8795>
2021-02-16 23:43:43 +00:00
Mike Blumenkrantz d550c5780f zink: use nir_shader_instructions_pass for draw params pass
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9090>
2021-02-16 18:13:31 -05:00
Jesse Natalie f95afdd606 clover: Add -fgnu89-inline to Clang command line
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9085>
2021-02-16 22:11:21 +00:00
Jesse Natalie 37142847fa microsoft/clc: Add test with inline function
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9085>
2021-02-16 22:11:21 +00:00
Jesse Natalie c1b8629b2c microsoft/clc: Add -fgnu89-inline to clang args
Without this, inline functions don't have their body emitted in the
resulting LLVM IR, meaning the kernel will fail to link.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9085>
2021-02-16 22:11:21 +00:00
Jason Ekstrand 1ef04f56c1 spirv: Delete the impl for prototype-only functions
Previously, when we had a prototype-only function in SPIR-V, we would
compile it just fine and the function would have an impl that did
nothing.  This commit changes that so that the nir_function::impl is
NULL to indicate a prototype-only function.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9069>
2021-02-16 20:50:51 +00:00
Jason Ekstrand 9d1d55f0fd spirv: Store the nir_function in vtn_function
This is a better mapping as not all nir_functions have impls.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9069>
2021-02-16 20:50:51 +00:00
Mike Blumenkrantz 4a35d27b87 zink: add nir_intrinsic_memory_barrier_image handling
this is the last one

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9087>
2021-02-16 20:31:09 +00:00
SureshGuttula fc0eb6554b frontends/va : Fix memory leaks incase of error returns
Incase of error returns missed the free calls for config and context.
This patch handling in freeing them

Signed-off-by: SureshGuttula <sguttula@amd.com>
Reviewed-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8993>
2021-02-16 19:14:40 +00:00
Jesse Natalie f59e6ad5d7 CI: Use a sha for the Windows SPIRV-LLVM-Translator dependency
Acked-by: Daniel Stone (daniels@collabora.com)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9018>
2021-02-16 18:33:18 +00:00