Commit Graph

264 Commits

Author SHA1 Message Date
Marek Olšák 350bdda83d radeonsi: code style fix
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16215>
2022-05-03 11:11:08 -04:00
Marek Olšák 2d4067a6fb util: change util_format_snorm8_to_sint8 -> snorm_to_sint for radeonsi
Convert all SNORM formats to SINT.

This fixes SNORM blits for radeonsi.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16132>
2022-04-28 12:44:13 +00:00
jiadozhu c9097d8939 radeonsi: fix crash in flush_resource when used with buffers
glWaitSemaphoreEXT triggers si_flush_resource callback
on pipe buffer resources, which may cause segmentation fault.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
2022-02-22 11:41:04 +00:00
Pierre-Eric Pelloux-Prayer 413bf889e7 radeonsi/blit: relax conditions to use sdma copy for prime buffers
We don't need to check if it's imported: PIPE_BIND_DRI_PRIME is enough.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14615>
2022-02-08 00:13:07 +00:00
Pierre-Eric Pelloux-Prayer 18c38bf78f gallium: rename PIPE_BIND_DRI_PRIME
The new name PIPE_BIND_PRIME_BLIT_DST is more precise.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14615>
2022-02-08 00:13:07 +00:00
Pierre-Eric Pelloux-Prayer 573d645133 radeonsi: fix fast clear / depth decompression corruption
Insert a flush after a depth decompression pass if the texture
was fast cleared.
This fixes a corruption which seems to only affect gfx10.3 chips.

Ideally we should also clear tex->need_flush_after_depth_decompression
after a flush but there's no easy way for this so this commit will
introduce extra flushes.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089>
2021-12-13 09:13:46 +00:00
Marek Olšák ba6d389fa7 radeonsi: don't use GS SGPR6 for the small prim cull info
use a user SGPR instead. This will be needed in the future.

Also don't upload small_prim_precision because it's passed via
VS_STATE_BITS.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13811>
2021-11-16 19:41:07 +00:00
Marek Olšák 6d483fed85 gallium/u_blitter: disable sample shading for all blits
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13602>
2021-11-04 15:06:09 +00:00
Marek Olšák 7ce3f8e639 gallium/util: fix util_can_blit_via_copy_region with unbound render condition
It returned false when a render condition was not bound, but it should
have returned true.

The bool stuff is random and incomplete, but that's life.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13602>
2021-11-04 15:06:09 +00:00
Pierre-Eric Pelloux-Prayer ec2eff8f38 radeonsi: use PIPE_BIND_DRI_PRIME instead of is_dri_blit_image
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13362>
2021-10-18 17:16:53 +02:00
Pierre-Eric Pelloux-Prayer 1863b761a6 radeonsi/gfx10.3: enable SDMA for DRI_PRIME copies
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13362>
2021-10-18 17:16:53 +02:00
Pierre-Eric Pelloux-Prayer a1dea665d0 radeonsi: make the DRI_PRIME dGPU -> iGPU copy async
Doing this copy using SDMA frees up the dGPU to do more
interesting things while the copy is happening; for instance
the rendering of the next frame.

hw queue activity before:
------------------------
dGPU:
  gfx: [renderframe 1][copy->iGPU][renderframe 2][copy->iGPU]...
iGPU:
  gfx:                            [Xorg]                    [Xorg]

hw queue activity before after:
------------------------------
dGPU:
  gfx: [renderframe 1][renderframe 2][renderframe 3]....
 sdma:                [copy->iGPU]  [copy->iGPU]   [copy->iGPU]
iGPU:
  gfx:                           [Xorg]        [Xorg] ...

If SDMA isn't available or can't do the copy, use an async compute
context instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12763>
2021-10-07 09:21:05 +00:00
Marek Olšák 3ea3621b8d radeonsi: determine num_vbos_in_user_sgprs from template arguments in draw_vbo
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Dave Airlie 3235b695b2 u_blitter: add support for sample0 only resolves.
This adds support for sample0 only resolves to support lavapipe

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12504>
2021-08-31 23:26:45 +00:00
Marek Olšák 804e292440 radeonsi: remove the separate DCC optimization for Stoney
This removes some complexity from the driver.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10343>
2021-04-26 22:53:30 +00:00
Marek Olšák 4d7dd094e3 radeonsi: fix automatic DCC retiling after DCC clear and DCC decompression
Fixes: d4f7962d48 - radeonsi: Add displayable DCC flushing without explicit flushes.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
2021-04-17 02:37:49 +00:00
Marek Olšák 8b95f51ef1 radeonsi: fix and enable full DCC with MSAA 2x on gfx9
This enables fast clear with any clear color (not just 0/1) for bpp >= 32.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
2021-04-13 03:17:42 +00:00
Marek Olšák ec42f52013 radeonsi: allow DCC_DECOMPRESS via CB with MSAA textures
The shader-based codepath doesn't support it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
2021-04-13 03:17:42 +00:00
Marek Olšák 8277732358 radeonsi: try to fix DCC coherency issues with DCC decompression
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
2021-04-13 03:17:42 +00:00
Marek Olšák faf10bd49d ac/surface: use named "color and "zs" structures in unions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
2021-04-12 20:53:45 +00:00
Marek Olšák 468836317b ac/surface: unify htile_* and dcc_* fields as meta_* fields
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
2021-04-12 20:53:45 +00:00
Marek Olšák 0580d4c1a2 radeonsi: enable HTILE with mipmapping on gfx9+
Everything seems to be there except fast clears.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 8cd61d1248 radeonsi: parallelize CMASK and DCC clears
Clearing 8 RTs with both DCC and CMASK caused 16 synchronized clears where
we also did 16 times WAIT_REG_MEM for CB flushes that were 15 times
useless.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 207bafd4dd radeonsi: reduce syncing in si_dcc_decompress
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 7e2b5ce722 radeonsi: set compute/cpdma sync flags in the outermost caller
This allows us to control syncing everywhere.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák e5ea9a3baa radeonsi: add a fast path for MSAA resolving with RGB -> BGR swizzling
When we encounter a situation when we need to swizzle, which the CB can't
resolve in one pass, swap the channel order on the next clear, so that we
don't have to swizzle.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9615>
2021-03-19 16:05:03 +00:00
Dave Airlie 8027a7ba8a shader_info: convert textures_used to a bitset.
For now keep it a bitset of 1 32-bit dword.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9456>
2021-03-10 06:16:09 +10:00
Pierre-Eric Pelloux-Prayer 90d6365ad4 radeonsi: force dcc clear to use compute clear
After the previous commit, when running the following
deqp-gles31 caselist:

  dEQP-GLES31.functional.image_load_store.2d.format_reinterpret.rgba32f_rgba32ui
  dEQP-GLES31.functional.image_load_store.2d.format_reinterpret.rgba32f_rgba32i

The second test always fails on gfx10. I don't know why,
but forcing the dcc clear from si_decompress_dcc to use
compute fixes the problem.

The test caselist wasn't failing before because the dcc
disable step was done in si_resource_copy_region, before
calling si_compute_copy_image.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8958>
2021-02-17 14:57:26 +01:00
Pierre-Eric Pelloux-Prayer 1d64a1045e radeonsi: enable dcc image stores on gfx10+
This was implemented in 1d3bffaf9c,
but missing the WRITE_COMPRESS_ENABLE bit, then disabled by
4dc6ed2a59040f04648eadbffeb1522587d00f3.

This commits reimplements it to:
- avoid disabling dcc when uploading FP16 textures
  (see si_use_compute_copy_for_float_formats)
- being able to use compute to upload textures in more cases, rather
  than using the blit path

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8958>
2021-02-17 14:57:26 +01:00
Pierre-Eric Pelloux-Prayer f18bceac72 radeonsi: replace force_cp_dma arg of si_clear_buffer by enum
The new enum has 3 values:
 - SI_CP_DMA_CLEAR_METHOD: equivalent to force_cp_dma = true
 - SI_COMPUTE_CLEAR_METHOD: to force the clear to use compute
 - SI_AUTO_SELECT_CLEAR_METHOD: equivalent to force_cp_dma = false

No functional change yet, but this will be used later.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8958>
2021-02-17 14:57:26 +01:00
Pierre-Eric Pelloux-Prayer a67d3e7c9e radeonsi: fix si_check_render_feedback
si_check_render_feedback only relied on si_images::enabled_mask and
si_samplers::enabled_mask to determine if a texture was being used
both as input and output.

Given that some samplers/images can be considered active (so accounted
for by enabled_mask) but not used by the current shader this could
lead to false-positive.

This commit fixes this by and-ing the above mask with the information
from shader_info for each active shader.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4227
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8869>
2021-02-17 09:11:46 +00:00
Pierre-Eric Pelloux-Prayer a8373b3d38 radeonsi: store si_context::xxx_shader members in union
This allows to access them individually (sctx->shader.ps) or
using array indexing (sctx->shaders[PIPE_SHADER_FRAGMENT]).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8869>
2021-02-17 09:11:46 +00:00
Pierre-Eric Pelloux-Prayer f2d57d28ed radeonsi/sqtt: use more event identifier
Using event identifiers allows to add a bit more context to the RGP trace.
Without this all draw calls are identified as vkCmdDraw.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8746>
2021-01-29 08:44:11 +00:00
Marek Olšák 5013828863 radeonsi: don't set vertex buffer dirty flags when they don't do anything
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8653>
2021-01-22 16:45:30 +00:00
Marek Olšák ca2062a394 radeonsi: simplify determining whether render condition is enabled at draw time
Read one bool instead of reading one bool and one pointer.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8653>
2021-01-22 16:45:30 +00:00
Marek Olšák 1a2dde8f86 radeonsi: add internal blitter_running flag
to skip the indirection in si_decompress_textures

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8653>
2021-01-22 16:45:30 +00:00
Marek Olšák 1f31a21664 radeonsi: remove SDMA support
There are many issues with SDMA across many generations of hardware.
A recent example is that gfx10.3 suffers from random GPU hangs if
userspace uses SDMA.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7908>
2020-12-09 00:52:26 +00:00
Bas Nieuwenhuizen d4f7962d48 radeonsi: Add displayable DCC flushing without explicit flushes.
Flushes non-explicit shared textures that need retiling on

* glFlush
* glSync
* glSignalSemaphoreEXT
* DRI fences.
* The first time we create a non-explicit handle for it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>
2020-11-13 03:27:28 +00:00
Pierre-Eric Pelloux-Prayer 5e4aecec93 radeonsi: introduce SI_RESOURCE_FLAG_INTERNAL / RADEON_FLAG_DRIVER_INTERNAL
Tag allocations as driver internal.
Some of these allocations will need to be doubled to handle TMZ (one secure bo,
one normal bo) but these allocations shouldn't switch the winsys in "the app
is using TMZ".

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6049>
2020-09-24 14:51:16 +00:00
Pierre-Eric Pelloux-Prayer 0294eaed80 radeonsi: extend workaround for KHR-GL45.texture_view.view_classes on gfx9
This is a followup of 19db1a540c.
This commit fixed KHR-GL45.texture_view.view_classes on gfx9 but the test
still failed when using AMD_DEBUG=nodma or AMD_DEBUG=nodcc,nodma.

The workaround is now used from si_resource_copy_region so it covers the
previous call site (si_texture_transfer_map) and the sctx->dma_copy
fallback code.

Fixes: 19db1a540c ("radeonsi: add a workaround to fix KHR-GL45.texture_view.view_classes on gfx9")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6115>
2020-08-05 19:45:32 +00:00
Marek Olšák d30e1e486d radeonsi: don't enable TC-compatible HTILE for stencil if stencil doesn't use it
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
2020-05-23 03:45:09 -04:00
Marek Olšák b5ac9d18d8 radeonsi: use vi_dcc_enabled instead of using tex->surface.dcc_offset directly
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
2020-05-15 22:12:35 +00:00
Marek Olšák 0d83e7f4b9 radeonsi: enable TC-compatible HTILE on demand for best Z/S performance
I haven't measured this, but it can only help.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4866>
2020-05-05 16:27:29 +00:00
Marek Olšák d6acdbd935 radeonsi: implement and use compute-based DCC decompression on gfx9-10
DCC_DECOMPRESS doesn't work. Instead of trying to figure out why,
use a compute blit where the load is compressed and the store is
uncompressed.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
2020-04-30 22:27:31 +00:00
Pierre-Eric Pelloux-Prayer d7008fe46a radeonsi: switch to 3-spaces style
Generated automatically using clang-format and the following config:

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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
2020-03-30 11:05:52 +00:00
Marek Olšák df34fa14bb radeonsi: don't invoke decompression inside internal launch_grid
Decompress resources properly but don't do it inside launch_grid
to prevent recursion.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
2020-01-20 15:40:08 -05:00
Pierre-Eric Pelloux-Prayer 7b0b085c94 radeonsi: drop the negation from fmask_is_not_identity
This change eases code reading ("fmask_is_identity = true" is clearer than
"fmask_is_not_identity = false").
Initialization is not changed so fmask_is_identity is false when a texture is
created.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
2020-01-15 10:10:15 +00:00
Pierre-Eric Pelloux-Prayer c2df5389bb radeonsi: make sure fmask expand is done if needed
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2248
Fixes: 095a58204d ("radeonsi: expand FMASK before MSAA image stores are used")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
2020-01-15 10:10:15 +00:00
Marek Olšák 363b4027fc radeonsi: put up to 5 VBO descriptors into user SGPRs
gfx6-8: 1 VBO descriptor in user SGPRs
gfx9-10: 5 VBO descriptors in user SGPRs

We no longer pull up to 5 VBO descriptors from GTT when SDMA is disabled.

Totals from affected shaders:
SGPRS: 1110528 -> 1170528 (5.40 %)
VGPRS: 952896 -> 951936 (-0.10 %)
Spilled SGPRs: 83 -> 61 (-26.51 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 23766296 -> 22843920 (-3.88 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 179344 -> 179344 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
Marek Olšák 269953e779 radeonsi/gfx9: force the micro tile mode for MSAA resolve correctly on gfx9
Fixes: 69ea473 "amd/addrlib: update to the latest version"
Closes: #2325

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-09 16:28:28 -05:00