We always have stage == first and stage == last when first == last, so
drop the special case. Also rephrase the comment to make the logic
clearer.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
This is helpful in debugging varying assignments.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
From Vulkan spec, 4.2.1. "Device Creation":
"vkCreateDevice verifies that extensions and features requested in
the ppEnabledExtensionNames and pEnabledFeatures members of
pCreateInfo, respectively, are supported by the implementation."
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@gmail.com>
SPIR-V tessellation shaders that were created from HLSL will have
the primitive generation domain set in tessellation control shader
(hull shader in HLSL) instead of the tessellation evaluation shader.
v2:
- Add assert (Kenneth)
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This patch limits the number of items on the fence work queue (the
deferred deletion list) by submitting a sync fence when the queue size
exceeds a threshold. This initiates deferred deletion of all resources
on the list and decreases the total amount of memory held waiting for
"deferred deletion".
This resolves bug 101467 filed against swr for the piglit
streaming-texture-leak test. For those running on smaller memory
(16GB?) systems, this will prevent oom-killer.
Thus far, we have not seen any real world applications that exhibit
behavior like the streaming-texture-leak test; as any form of pipeline
flush will trigger the defer queue and properly free any retained
allocations. But, this addresses those as well.
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
We lost some precision on a previous change due to switching to
integers. Since we report a float in timestampPeriod, we want the
division to happen in floats.
CID: 1413021
Fixes: c77d98ef32 ("intel: common: express timestamps units in frequency")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
In particular Shader Channel Select & Texture Address Control Mode.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Being able to see the access mode of various mappings is incredibly
useful for debugging. With this patch, INTEL_DEBUG=buf now shows
data such as:
bo_create: buf 7 (bufferobj) 640b
bo_map_gtt: 7 (bufferobj) -> 0x7fca1fae5000, WRITE ASYNC
brw_bo_map_cpu: 7 (bufferobj) -> 0x7fca1fae4000, READ
bo_map_gtt: 5 (bufferobj) -> 0x7fca1fad4000, WRITE ASYNC
brw_bo_map_cpu: 7 (bufferobj) -> 0x7fca1fae4000, READ
which makes it easy to see that there are async GTT writes with
intervening CPU reads.
Reviewed-by: Matt Turner <mattst88@gmail.com>
With the conversion to storing the result of drm_mmap to a local and not
directly to bo->map_gtt itself, we no longer should clear bo->map_gtt.
In the best the operation is redundant as we know bo->map_gtt to already
be NULL, but in the worst case we overwrite a concurrent thread that
successfully mmaped the GTT.
Fixes: 314647c4c2 ("i965: Drop global bufmgr lock from brw_bo_map_* functions.")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
After removing the unusuable debugging code in the previous commit, we
can also entirely remove the global mutex around mapping the buffer for
the first time and replace it with a single atomic operation to update
the cache once we retrieve the mmap.
v2 (Ken): Split out from Chris's original commit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
With the broken debugging code gone, it doesn't do anything anymore.
We could technically eliminate it, but I'd like to keep it around in
case we want to add something there again someday. Otherwise we'd
have to go all over the codebase adding unmap calls back again.
Based on a patch by Chris Wilson.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Supposedly we were keeping a reference count for the number of users of
a mapping so that we could use valgrind to detect access to the map
outside of the valid section. However, we were incrementing the counter
only when first creating the cached mapping but decrementing on every
unmap. The bo->map_count tracking was wrong and so the debugging code
was completely useless.
v2 (Ken): Separate out atomic compare and swap optimization.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
At first glance this seems missing, since we handle it manually for CPU
and WC maps. Although a bit inconsistent, it's actually not necessary.
Thanks to Chris Wilson for explaining this to me.
Reviewed-by: Matt Turner <mattst88@gmail.com>
We apparently still used v16i8 ....
As radeonsi doesn't use it with LLVM version checks I don't think
we need them either.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
The state tracker should never ask us to create a texture with invalid
dimensions / mipmap levels. Do some assertions to check that.
No Piglit regressions.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
If we're rendering to an incomplete/inconsistent (cube) texture, the
different faces/levels of the texture may be stored in different
resources. Before, we always used the texture object resource. Now,
we use the texture image resource. In normal circumstances, that's
the same resource. But in some cases, such as the Piglit
fbo-incomplete-texture-03 test, the cube faces are in different
resources and we need to render to the texture image resource.
Fixes fbo-incomplete-texture-03 with VMware driver.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Return early from st_finalize_texture() if we have an incomplete
texture. This avoids trying to create a texture resource with invalid
parameters (too many mipmap levels given the base dimension).
Specifically, the Piglit fbo-incomplete-texture-03 test winds up
calling pipe_screen::resource_create() with width0=32, height0=32 and
last_level=6 because the first five cube faces are 32x32 but the sixth
face is 64x64. Some drivers handle this, but others (like VMware svga)
do not (generates device errors).
Note that this code is on the path that's usually not taken (we normally
build consistent textures).
No Piglit regressions.
v2: only need to check for base-level completeness since that's what has to
be consistent in order to specify the dimensions for a new gallium texture.
Per Roland.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Commit 8aba778fa2 "st/mesa: don't set
sampler states for TBOs" changed how texture buffer objects are handled.
Document the new convention.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Take the CL pointer in, which will be useful for enabling relocs.
However, our code expands a bit more:
before:
4449 0 0 4449 1161 src/gallium/drivers/vc4/.libs/vc4_draw.o
988 0 0 988 3dc src/gallium/drivers/vc4/.libs/vc4_emit.o
after:
4481 0 0 4481 1181 src/gallium/drivers/vc4/.libs/vc4_draw.o
1020 0 0 1020 3fc src/gallium/drivers/vc4/.libs/vc4_emit.o
I really liked this idea, as it should help with management of packet
parsing tools like the CL dump. The python script is forked off of theirs
because our packets are byte-based instead of dwords, and the changes to
do so while avoiding performance regressions due to unaligned accesses
were quite invasive.
v2: Fix Android.mk paths, drop shebang for python script, fix overlap
detection.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Rob Herring <robh@kernel.org>
In swr_update_derived, for consistency, index buffer validation should
be using the p_draw_info copy "info" rather than referencing
p_draw_info.
No functional change.
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Tag pStat field in swr_draw_context structure so gen_llvm_types.py
can deal with the actual structure type instead of using void.
Code cleanup, no functional change.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Switch from a macro-based simd intrinsics layer to a more C++
implementation, which also adds AVX512 optimizations to 128-bit
and 256-bit SIMD.
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
Each shader stage state (VS, TS, GS, SO, BE/CLIP) now has a
vertexAttribOffset to specify the offset to the start of the
general attribute section of the incoming verts for that stage.
It is up to the driver to set this up correctly based on the
active stages. All the shader stages use this value instead of
VERTEX_ATTRIB_START_SLOT to offset to the incoming attributes.
Only the vertex shader stage supports dynamic layout output
currently. The other stages continue to expect the output to be
the fixed layout slots as before. Will be enabling GS next.
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
There is typo in the mkdir command path,
the correct one is $(TARGET_OUT)/$(l)/$(MESA_DRI_MODULE_REL_PATH)
The other issue is in 32bit builds, because lib64 does not exist there,
we can use TARGET_IS_64_BIT to refine the post install command.
Fixes: a3d98ca62f ("Android: use symlinks for driver loading")
Signed-off-by: Rob Herring <robh@kernel.org>
Nicolai Hähnle
Samuel Iglesias Gonsálvez
Bruce Cherniak
Lionel Landwerlin
Kenneth Graunke
Chris Wilson
Bas Nieuwenhuizen
Brian Paul
Eric Anholt
Tim Rowley
Andres Gomez
Mauro Rossi