39800f0fa3
amd: change chip_class naming to "enum amd_gfx_level gfx_level"
...
This aligns the naming with PAL.
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469 >
2022-05-13 14:56:22 -04:00
529eb739fc
radeonsi/gfx11: add CB deltas
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328 >
2022-05-10 04:29:54 +00:00
01d994f5e6
radeonsi: add color buffer support for R9G9B9E5_FLOAT on gfx10.3
...
This was missed when we added gfx10.3.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16215 >
2022-05-03 11:11:08 -04:00
7341cb7654
radeonsi: fix ALPHA_IS_ON_MSB determination
...
based on PAL
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15965 >
2022-04-22 20:52:26 +00:00
0136545d16
radeonsi: add check for graphics to si_try_normal_clear
...
Cc: mesa-stable
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15177 >
2022-03-01 19:05:06 +00:00
f865631b1b
radeonsi: replace SI_RESOURCE_FLAG_UNMAPPABLE with PIPE_RESOURCE_FLAG_UNMAPPABLE
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098 >
2022-02-22 11:41:04 +00:00
d84e0096a5
radeonsi/gfx8: use the proper dcc clear size
...
dcc_fast_clear_size is assigned using addrlib's dccFastClearSize, which
is computed using the whole surface size (including layers) so we don't
need to multiply dcc_fast_clear_size by num_layers.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4530
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14409 >
2022-01-06 09:25:57 +01:00
84fea554e3
radeonsi: silence a warning
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089 >
2021-12-13 09:13:46 +00:00
573d645133
radeonsi: fix fast clear / depth decompression corruption
...
Insert a flush after a depth decompression pass if the texture
was fast cleared.
This fixes a corruption which seems to only affect gfx10.3 chips.
Ideally we should also clear tex->need_flush_after_depth_decompression
after a flush but there's no easy way for this so this commit will
introduce extra flushes.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089 >
2021-12-13 09:13:46 +00:00
56382ec071
radeonsi: unreference framebuffer state after use
...
util_copy_framebuffer_state increases refcounts, so we have
to decrement them afterwards.
Fixes: b1b491cdbbhttps://gitlab.freedesktop.org/mesa/mesa/-/issues/5631
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13838 >
2021-11-18 10:53:34 +01:00
74adf22a0a
radeonsi: fix a typo preventing a fast depth-stencil clear
...
Fixes: 9defe8aca9https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13603 >
2021-11-04 17:36:26 +00:00
3baeaac64b
radeonsi: rename stencil_cleared_level_mask -> stencil_cleared_level_mask_once
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13603 >
2021-11-04 17:36:26 +00:00
b1b491cdbb
radeonsi: add a faster clear path for glClearTexImage
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13603 >
2021-11-04 17:36:26 +00:00
5d3aea49b8
radeonsi: fix 2 issues with depth_cleared_level_mask
...
- Unset depth_cleared_level_mask for non-clear blits. Set the flag after
the clear, so that we don't have to check blitter_running.
- Set depth_cleared_level_mask only when we set depth_clear_value.
Fixes: ff8a930cf7https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13603 >
2021-11-04 17:36:26 +00:00
c494cfb1dd
radeonsi: don't invoke si_decompress_depth if textures are not dirty at binding
...
This eliminates the overhead of invoking si_decompress_depth.
The complication here is that we need to update needs_depth_decompress_mask
every time we update dirty_level_mask.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13492 >
2021-10-29 07:14:33 +00:00
cb845c53f4
radeonsi: enable DCC stores for clear_render_target on gfx10
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449 >
2021-09-01 07:51:30 +00:00
e6d996f8ff
radeonsi: improve rounding of zmin
...
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12389 >
2021-08-17 01:09:51 +00:00
b72c7c6c56
radeonsi: fix fb_too_small condition
...
fb->num_layers can be 0 so use util_num_layers(tex) instead.
Fixes: f7c58559f5https://gitlab.freedesktop.org/mesa/mesa/-/issues/4764
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11625 >
2021-06-29 23:38:21 +02:00
ff8a930cf7
radeonsi: add _once suffix to depth_cleared_level_mask
...
And add a new variable to disambiguate between "has been cleared once" and
"is cleared".
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979 >
2021-06-15 10:19:02 +02:00
36e07198a7
radeonsi: always use the L2 LRU cache policy for faster clears and copies
...
Waves and CP DMA can finish sooner if L2 doesn't do any evictions, which
is hard to predict.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813 >
2021-05-25 16:15:44 +00:00
804e292440
radeonsi: remove the separate DCC optimization for Stoney
...
This removes some complexity from the driver.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10343 >
2021-04-26 22:53:30 +00:00
4d7dd094e3
radeonsi: fix automatic DCC retiling after DCC clear and DCC decompression
...
Fixes: d4f7962d48https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261 >
2021-04-17 02:37:49 +00:00
3120113ee7
radeonsi: implement DCC MSAA 4x/8x fast clear using DCC equations on gfx9
...
MSAA 4x and 8x should only clear the first 2 samples because other samples
are uncompressed. The compute shader only clears that subset of DCC.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
8b95f51ef1
radeonsi: fix and enable full DCC with MSAA 2x on gfx9
...
This enables fast clear with any clear color (not just 0/1) for bpp >= 32.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
f7c58559f5
radeonsi: refine fast clears for small buffers, always use them for large HTILE
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
06b6af596c
radeonsi: do Z-only or S-only HTILE clear using a compute shader doing RMW
...
This adds a clear_buffer compute shader that does read-modify-write to
update a subset of bits in HTILE.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
84fa21a611
radeonsi: when transitioning to TC-compat HTILE, try to do a proper clear
...
instead of always clearing to uncompressed.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
558ab3310d
radeonsi: enable DCC fast clears for non-zero mipmap levels and 0/1 clear values
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
9defe8aca9
radeonsi: implement fast Z/S clears using clear_buffer on HTILE
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
e2714d5dd4
radeonsi: indent the code for TC-compatibility HTILE transition
...
So that HTILE clears can be nicely inserted into a new else statement there.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
fcd01ad444
radeonsi: add si_can_fast_clear_depth/stencil helpers
...
for later use
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
4dd8d58ad5
radeonsi: clean up some mess around htile_stencil_disabled
...
Set the final value in si_texture_create_object, so that other places
don't have to derive it redundantly.
The only thing to remember is that HTILE stencil can be enabled when
stencil is not present, and it can be disabled when stencil is present
due to various workarounds.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
bcd1a69f79
radeonsi: parallelize Z/S conversion into TC-compatible with fast color clears
...
It's not really a fast clear, but it's the next logical step towards doing
HTILE clears here.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
fb72d41b18
radeonsi: implement Z/S fast clear for non-zero mipmap levels
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
6434b0b652
radeonsi: implement per-level DCC and CMASK fast clears for gfx10+
...
Fast clears are only used for level 0. This enables clearing level 0
of CMASK and DCC on gfx10+ when there are multiple mipmap levels.
vi_dcc_clear_level can also clear any level now.
Mipmapped array textures are still cleared slowly.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
059f042fb1
radeonsi: allow trivial DCC clears for shared textures with DCC constant encode
...
This relaxes the existing restriction.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003 >
2021-04-13 03:17:42 +00:00
faf10bd49d
ac/surface: use named "color and "zs" structures in unions
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083 >
2021-04-12 20:53:45 +00:00
468836317b
ac/surface: unify htile_* and dcc_* fields as meta_* fields
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083 >
2021-04-12 20:53:45 +00:00
ab00557685
ac/surface: pack alignments by storing log2 in radeon_surf
...
Only one bit is set in alignments, so store the bit offset (log2) and
change the type from uint32_t to uint8_t.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083 >
2021-04-12 20:53:45 +00:00
3f074d2f45
ac/surface: inline and reorder gfx9_surf_flags for better packing
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083 >
2021-04-12 20:53:45 +00:00
2fd8018845
ac/surface: split dcc level info from surface_info to save space
...
stencil level info doesn't have DCC
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083 >
2021-04-12 20:53:45 +00:00
64cbab5348
radeonsi: turn the loops over color buffers into while loops in si_clear
...
NULL color buffers are not set in "buffers" here.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795 >
2021-04-02 12:05:00 +00:00
5ba77c4a5d
radeonsi: unset PIPE_CLEAR_* flags for non-existent buffers
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795 >
2021-04-02 12:05:00 +00:00
0580d4c1a2
radeonsi: enable HTILE with mipmapping on gfx9+
...
Everything seems to be there except fast clears.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795 >
2021-04-02 12:05:00 +00:00
3345e32de7
radeonsi: group and parallelize all clears in si_texture_create_object
...
This reduces aux_context flushes significantly.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795 >
2021-04-02 12:05:00 +00:00
cb6e1c7c11
radeonsi: add num_layers variable into si_do_fast_color_clear
...
in preparation for the next commit
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795 >
2021-04-02 12:05:00 +00:00
1936a046b1
radeonsi: return success/failure from si_alloc_separate_cmask
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795 >
2021-04-02 12:05:00 +00:00
8cd61d1248
radeonsi: parallelize CMASK and DCC clears
...
Clearing 8 RTs with both DCC and CMASK caused 16 synchronized clears where
we also did 16 times WAIT_REG_MEM for CB flushes that were 15 times
useless.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795 >
2021-04-02 12:05:00 +00:00
7e2b5ce722
radeonsi: set compute/cpdma sync flags in the outermost caller
...
This allows us to control syncing everywhere.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795 >
2021-04-02 12:05:00 +00:00
e5ea9a3baa
radeonsi: add a fast path for MSAA resolving with RGB -> BGR swizzling
...
When we encounter a situation when we need to swizzle, which the CB can't
resolve in one pass, swap the channel order on the next clear, so that we
don't have to swizzle.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9615 >
2021-03-19 16:05:03 +00:00
Marek Olšák
Thong Thai
Pierre-Eric Pelloux-Prayer
Filip Gawin