Commit Graph

39823 Commits

Author SHA1 Message Date
Nicolas Kaiser 71fd35d1ad nv50: fix always true conditional in shader optimization 2010-10-05 18:53:15 +02:00
Jerome Glisse 585e4098aa r600g: improve bo flushing
Flush read cache before writting register. Track flushing inside
of a same cs and avoid reflushing same bo if not necessary. Allmost
properly force flush if bo rendered too and then use as a texture
in same cs (missing pipeline flush dunno if it's needed or not).

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-05 10:43:23 -04:00
Jerome Glisse 12d16e5f14 r600g: store reloc information in bo structure
Allow fast lookup of relocation information & id which
was a CPU time consumming operation.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-05 10:42:56 -04:00
Dave Airlie bf21b7006c pb: fix numDelayed accounting
we weren't decreasing when removing from the list.
2010-10-05 19:08:41 +10:00
Dave Airlie 12be1568d0 r600g: avoid unneeded bo wait
if we know the bo has gone not busy, no need to add another bo wait

thanks to Andre (taiu) on irc for pointing this out.
2010-10-05 16:00:48 +10:00
Dave Airlie d2c06b5037 r600g: drop use_mem_constant.
since we plan on using dx10 constant buffers everywhere.
2010-10-05 16:00:23 +10:00
Dave Airlie 46997d4fc2 r600g: drop mman allocator
we don't use this since constant buffers are now being used on all gpus.
2010-10-05 15:57:57 +10:00
Dave Airlie 05813ad5f4 r600g: add bo busy backoff.
When we go to do a lot of bos in one draw like constant bufs we need
to avoid bouncing off the busy ioctl, this mitigates by backing off
on busy bos for a short amount of times.
2010-10-05 15:51:38 +10:00
Dave Airlie 49866c8f34 pb: don't keep checking buffers after first busy
If we assume busy buffers are added to the list in order its unlikely
we'd fine one after the first busy one that isn't busy.
2010-10-05 15:50:58 +10:00
Dave Airlie 3c38e4f138 r600g: add bo fenced list.
this just keeps a list of bos submitted together, and uses them to decide
bo busy state for the whole group.
2010-10-05 15:35:52 +10:00
Brian Paul fb5e6f88fc swrast: fix choose_depth_texture_level() to respect mipmap filtering state
NOTE: this is a candidate for the 7.9 branch.
2010-10-04 19:59:46 -06:00
Marek Olšák d0408cf55d r300g: fix microtiling for 16-bits-per-channel formats
These texture formats (like R16G16B16A16_UNORM) were untested until now
because st/mesa doesn't use them. I am testing this with a hacked st/mesa
here.
2010-10-05 02:57:00 +02:00
Marek Olšák 57b7300804 update release notes for Gallium
I am trying to be exhaustive, but still I might have missed tons of other
changes to Gallium.
(cherry picked from commit 968a9ec76eadf55e8b58171884e1175d7b8cf59a)

Conflicts:

	docs/relnotes-7.9.html
2010-10-05 02:56:59 +02:00
Ian Romanick 4d435c400d docs: Add list of bugs fixed in 7.9 2010-10-04 17:39:48 -07:00
Eric Anholt ea909be58d i965: Add support for gen6 FB writes to the new FS.
This uses message headers for now, since we'll need it for MRT.  We
can cut out the header later.
2010-10-04 16:08:17 -07:00
Eric Anholt 739aec39bd i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod.
It instead sensibly appears in the src0 slot.
2010-10-04 16:08:17 -07:00
Eric Anholt 3bf8774e9c i965: Add initial folding of constants into operand immediate slots.
We could try to detect this in expression handling and do it
proactively there, but it seems like less logic to do it in one
optional pass at the end.
2010-10-04 16:08:17 -07:00
Eric Anholt e27c88d8e6 i965: Add trivial dead code elimination in the new FS backend.
The glsl core should be handling most dead code issues for us, but we
generate some things in codegen that may not get used, like the 1/w
value or pixel deltas.  It seems a lot easier this way than trying to
work out up front whether we're going to use those values or not.
2010-10-04 16:08:17 -07:00
Eric Anholt 9faf64bc32 i965: Be more conservative on live interval calculation.
This also means that our intervals now highlight dead code.
2010-10-04 16:08:17 -07:00
Vinson Lee a0a8e24385 r600g: Fix SCons build. 2010-10-04 15:56:55 -07:00
Jerome Glisse b25c52201b r600g: remove dead label & fix indentation
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04 17:25:19 -04:00
Jerome Glisse 243d6ea609 r600g: rename radeon_ws_bo to r600_bo
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04 17:25:19 -04:00
Jerome Glisse 674452faf9 r600g: use r600_bo for relocation argument, simplify code
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04 17:25:19 -04:00
Jerome Glisse d22a1247d8 r600g: allow r600_bo to be a sub allocation of a big bo
Add bo offset everywhere needed if r600_bo is ever a sub bo
of a bigger bo.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04 17:25:19 -04:00
Jerome Glisse 294c9fce1b r600g: rename radeon_ws_bo to r600_bo
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04 17:25:19 -04:00
Krzysztof Smiechowicz 68c7994ab5 nvfx: Pair os_malloc_aligned() with os_free_aligned().
From AROS.
2010-10-04 11:43:29 -07:00
Dave Airlie 3d45d57044 r600g: TODO domain management
no wonder it was slow, the code is deliberately forcing stuff into GTT,
we used to have domain management but it seems to have disappeared.
2010-10-04 16:41:49 +10:00
Dave Airlie 1c2b3cb1e9 r600g: fix wwarning in bo_map function 2010-10-04 16:26:46 +10:00
Dave Airlie 6dc051557d r600g: the code to check whether a new vertex shader is needed was wrong
this code was memcmp'ing two structs, but refcounting one of them afterwards,
so any subsequent memcmp was never going to work.

again this stops unnecessary uploads of vertex program,
2010-10-04 16:24:59 +10:00
Dave Airlie 92aba9c1f5 r600g: break out of search for reloc bo after finding it.
this function was taking quite a lot of pointless CPU.
2010-10-04 15:58:39 +10:00
Eric Anholt 14bf92ba19 i965: Fix glean/texSwizzle regression in previous commit.
Easy enough patch, who needs a full test run.  Oh, that's right.  Me.
2010-10-03 00:24:09 -07:00
Eric Anholt a7fa00dfc5 i965: Set up swizzling of shadow compare results for GL_DEPTH_TEXTURE_MODE.
The brw_wm_surface_state.c handling of GL_DEPTH_TEXTURE_MODE doesn't
apply to shadow compares, which always return an intensity value.  The
texture swizzles can do the job for us.

Fixes:
glsl1-shadow2D(): 1
glsl1-shadow2D(): 3
2010-10-02 23:48:14 -07:00
Eric Anholt 4fb0c92c69 i965: Add support for EXT_texture_swizzle to the new FS backend. 2010-10-02 23:44:44 -07:00
Marek Olšák 8f7177e0de r300g: add support for L8A8 colorbuffers
Blending with DST_ALPHA is undefined. SRC_ALPHA works, though.
I bet some other formats have similar limitations too.
2010-10-02 23:19:38 +02:00
Marek Olšák e75bce026c r300g: add support for R8G8 colorbuffers
The hw swizzles have been obtained by a brute force approach,
and only C0 and C2 are stored in UV88, the other channels are
ignored.

R16G16 is going to be a lot trickier.
2010-10-02 21:42:22 +02:00
Dave Airlie 71a079fb4e mesa/st: initial attempt at RG support for gallium drivers
passes all piglit RG tests with softpipe.
2010-10-02 17:03:15 +10:00
Kenneth Graunke f317713432 i965: Fix incorrect batchbuffer size in gen6 clip state command.
FORCE_ZERO_RTAINDEX should be in the fourth (and final) dword.
2010-10-01 21:53:28 -07:00
Eric Anholt 64a9fc3fc1 i965: Don't try to emit code if we failed register allocation. 2010-10-01 17:19:04 -07:00
Eric Anholt 6397addd61 i965: Fix off-by-ones in handling the last members of register classes.
Luckily, one of them would result in failing out register allocation
when the other bugs were encountered.  Applies to
glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still
fails register allocation, but now legitimately.
2010-10-01 17:19:04 -07:00
Eric Anholt afb64311e3 i965: Add a sanity check for register allocation sizes. 2010-10-01 17:19:03 -07:00
Eric Anholt 5ee0941316 i965: When producing a single channel swizzle, don't make a temporary.
This quickly cuts 8% of the instructions in my glsl demo.
2010-10-01 17:19:03 -07:00
Eric Anholt a0799725f5 i965: Restore the forcing of aligned pairs for delta_xy on chips with PLN.
By doing so using the register allocator now, we avoid wasting a
register to make the alignment happen.
2010-10-01 17:19:03 -07:00
Alex Deucher fb0eed84ca r600c: fix segfault in evergreen stencil code
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=30551
2010-10-01 20:14:25 -04:00
Vinson Lee 7af2a22d1f r600g: Remove unnecessary headers. 2010-10-01 17:06:33 -07:00
Vinson Lee 20846a8ce1 r600g: Remove unused variable.
Fixes this GCC warning.
r600_shader.c: In function 'tgsi_split_literal_constant':
r600_shader.c:818: warning: unused variable 'index'
2010-10-01 17:02:01 -07:00
Ian Romanick 1ca6cbec1b rgtc: Detect RGTC formats as color formats and as compressed formats 2010-10-01 16:55:35 -07:00
Ian Romanick 5ebbabc5cc mesa: Trivial correction to comment 2010-10-01 16:55:35 -07:00
Ian Romanick 69c78bf2c2 mesa: Fix misplaced #endif
If FEATURE_texture_s3tc is not defined, FXT1 formats would erroneously
fall through to the MESA_FORMAT_RGBA_FLOAT32 case.
2010-10-01 16:55:35 -07:00
Ian Romanick 7c6147014a ARB_texture_rg: Add GL_COMPRESSED_{RED,RG} cases in _mesa_is_color_format 2010-10-01 16:55:35 -07:00
Ian Romanick e2a054b70c mesa: Add ARB_texture_compression_rgtc as an alias for EXT_texture_compression_rgtc
Change the name in the extension tracking structure to ARB (from EXT).
2010-10-01 16:55:35 -07:00