Commit Graph

99535 Commits

Author SHA1 Message Date
Timothy Arceri c6a0ce7e54 radeonsi/nir: add nir_intrinsic_load_sample_mask_in to ir scan
Fixes a bunch of ARB_sample_shading piglit tests.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-23 09:11:21 +11:00
Samuel Thibault 9131e6d3c2 u_thread: Use pthread_setname_np on linux only.
pthread_setname_np was added in glibc 2.12 for the Linux port only, other
ports do not necessarily have it.

Signed-off-by: Jose Fonseca <jfonseca@vmware.com>
2018-01-22 21:12:41 +00:00
Jose Fonseca dcbb224c68 svga: Prevent use after free.
Courtesy of clang static analyzer.

I was hunting for potential sources of memory corruption using Mesa with
a GL trace, and happened to find this (unrelated) issue.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2018-01-22 21:12:41 +00:00
Kenneth Graunke 60f15477da i965: Drop render_target_start from binding table struct.
We have to start render targets at binding table index 0 in order to use
headerless FB write messages, and in fact already assume this in a bunch
of places in the code.  Let's finish that off, and not bother storing 0
in a struct to pretend to add it in a few places.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-01-22 10:03:52 -08:00
Emil Velikov a9bb067e27 i965: make brw_context::num_samples unsigned int
It is never a negative number. Variable is compared against unsigned
values and passed into functions that expect unsigned int.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-01-22 16:31:57 +00:00
Emil Velikov ef1df63046 st/mesa: provide static inline st_init_vdpau_functions
The ifdef spaghetty in st_vdpau.c is rather confusing and misleading.
Simplily it by introducing a static inline helper noop (when
HAVE_ST_VDPAU is not defined) in the header.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-01-22 16:31:15 +00:00
Samuel Pitoiset 33e6e5e6a4 radv: add an option that allows to dump pre-optimization ir
With RADV_DEBUG=preoptir.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-22 12:28:33 +01:00
Chris Wilson 525b4f7548 i965: Accept CONTEXT_ATTRIB_PRIORITY for brwCreateContext
The forward port of commit 6d87500fe1 ("dri: Change
__DriverApiRec::CreateContext to take a struct for attribs") failed to
adapt the set of allowed attributes for the earlier introduction of
context priorities (commit 1617fca6d1 "i965: Pass the EGL/DRI context
priority through to the kernel").

Fixes: 6d87500fe1 ("dri: Change __DriverApiRec::CreateContext to take a struct for attribs")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Adam Jackson <ajax@redhat.com>
Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
2018-01-22 10:24:20 +00:00
Matthew Nicholls 005375717b radv: restore previous stencil reference after depth-stencil clear
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alex Smith <asmith@feralinteractive.com>
2018-01-22 08:57:42 +00:00
Jason Ekstrand 5048572352 i965: Set tiling on BOs imported with modifiers
We need this to ensure that GTT maps work on buffers we get from Vulkan
on the off chance that someone does a readpixels or something.  Soon, we
will be removing GTT maps from i965 entirely and this can be reverted.
None the less, it's needed for stable.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2018-01-21 23:07:18 -08:00
Jason Ekstrand b9e7b29705 i965/bufmgr: Add a create_from_prime_tiled function
This new function is an import and a set tiling in one go.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2018-01-21 23:07:18 -08:00
Jason Ekstrand ad424b2243 i965/miptree: Use the tiling from the modifier instead of the BO
This fixes a bug where we were taking the tiling from the BO regardless
of what the modifier said.  When we got images in from Vulkan where it
doesn't set the tiling on the BO, we would treat them as linear even
though the modifier expressly said to treat it as Y-tiled.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2018-01-21 23:07:18 -08:00
Jason Ekstrand 0465dd13d2 i965/miptree: Add an explicit tiling parameter to create_for_bo
Otherwise, create_for_bo will just grab the tiling from the BO which is
not what we want when using modifiers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2018-01-21 23:07:16 -08:00
Bas Nieuwenhuizen 4584c4ef04 radv: Don't allow 3d or 1d depth/stencil textures.
addrlib asserts when that happens, and supporting it is not
required so lets not allow this for now.

It also assert on fmask, but we don't have the number of samples here.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:43 +01:00
Bas Nieuwenhuizen 8b98929074 radv: Init variant entry with memset.
This gets memcpy'd and written driectly, and due to alignment, this
resulted in uninitialized gaps. This makes those gaps go away.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:39 +01:00
Bas Nieuwenhuizen fb0992e967 radv: Fix bufimage failure deallocation.
The inidividual init parts don't clean up their own stuff on failure.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:32 +01:00
Bas Nieuwenhuizen 2c802ca66c radv: Fix fragment resolve init memory allocation failure paths.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:29 +01:00
Bas Nieuwenhuizen c685076ab0 radv: Fix freeing meta state if the device pipeline cache fails to allocate.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:24 +01:00
Bas Nieuwenhuizen 71f0315a88 radv: Fix memory allocation failure path in compute resolve init.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:19 +01:00
Bas Nieuwenhuizen d956e0bdf5 radv: Fix ordering issue in meta memory allocation failure path.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:03 +01:00
Lucas Stach 29a0ea699a etnaviv: dirty TS state when framebuffer has changed
When switching between framebuffers with and without TS, the TS state
needs to be flushed to the command stream even if the derived state
isn't changed.

Fixes: 4ee7c2c284 ("etnaviv: enable TS, but disable autodisable")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-01-21 12:58:02 +01:00
Vinson Lee e03c880971 broadcom/vc5: Fix source file name.
Fixes: c9b2cb7897 ("vc5: add missing files to the tarball")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-01-21 11:13:16 +08:00
Vinson Lee 14abbe604b broadcom/vc5: Add missing include paths.
Fixes: 954a704da3 ("broadcom/vc5: Port the RCL setup to V3D4.1.")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-01-21 11:05:33 +08:00
Eric Anholt f398aa6aef mesa: Only require independent blending for GLES 3.2.
We've been requiring this since GLES 3.0 was introduced, but the GLES 3.2
spec is the one that has "Supporting blending on a per-draw-buffer basis"
in the new features.  V3D 3.3 would require lowering blending to shader
code to implement independent blending.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-01-21 10:48:00 +08:00
Kenneth Graunke 60d8fe9216 i965: Delete completely bogus comment
This hasn't been true in 6+ years, if it was even true then.  Before
we rewrote the compiler and introduced GLSL IR in 2010-2011, i965 used
to have two compiler backends for WM programs, based on Mesa IR.  One
handled flow control and was SIMD8-only, while the other was SIMD16
only and didn't handle flow control.  Or something like that.

Even then, this certainly didn't handle vertex shaders, so "all ...
code generation" is a bit strong.
2018-01-20 01:31:25 -08:00
Dylan Baker 436ed65d38 autotools: include meson build files in tarball
This adds the meson.build, meson_options.txt, and a few scripts that are
used exclusively by the meson build.

v2: - Remove accidentally included changes needed to test make dist with
      LLVM > 3.9

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-19 16:30:51 -08:00
George Kyriazis 9d80ed0862 swr/rast: Fix llvm5 behavior
For some reason llvm5 is picky about accepting a void * type in the
case of building an argument list.

Since we don't care about the type (we ignore the argument for now),
pick another pointer type

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 17:08:30 -06:00
George Kyriazis d335b32baf swr/rast: Enable early rasterization
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:43 -06:00
George Kyriazis bacfbe5a32 swr/rast: Implement Early Rasterization optimization
Early Rasterization is an optimization for small triangles.

Scientific workloads often contain very small triangles that has non-zero
area and cannot be trivially rejected as falling between pixel centers,
but does not cover any pixel center. Those triangles can be initially
rasterized as early as in binner and rejected if they cover no pixels The
optimization can be disabled in compilation using KNOB_ENABLE_EARLY_RAST
option in knobs.h

The Early Rast is disabled by default.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:43 -06:00
George Kyriazis be3cd7add1 swr/rast: Enable simd16 vertex shaders
Flip the switch(es) to enable simd16 vertex shaders:

USE_SIMD16_SHADERS and USE_SIMD16_VS

Both have to be enabled at the same time.  Currently, just setting
USE_SIMD16_SHADERS does not work correctly.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:42 -06:00
George Kyriazis 8c83d2d371 swr: Support simd16 vertex shaders
Supporting simd16 vertex shaders involves packing the output of the
fetch shader appropriately, especially the vertexID buffers that have to
be formatted in one simd16 register, needed by the VS.

As part of this support, we needed to remove the 2nd JitManager, since it
was not accounting for vector width correctly.

USE_SIMD16_SHADERS is also split into two defines.  The additional
one (USE_SIMD16_VS) controls the width of the vertex shader (VS), while
the original one (USE_SIMD16_SHADERS) controls overall front end width.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:42 -06:00
George Kyriazis 1874d95a8e swr/rast: changed jit debug magic number
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:41 -06:00
George Kyriazis c719f62621 swr/rast: Added ICLAMP builder function
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:41 -06:00
George Kyriazis f192502001 swr/rast: Jit debug work
Properly validate DLL matches OBJ for jitted function

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:41 -06:00
George Kyriazis 3c405e32b0 swr/rast: silence generated file warnings
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:40 -06:00
George Kyriazis fe107e3c17 swr/rast: jit shader lib debug work
Create shader_lib during build, link with shaders at DLL generation time

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:40 -06:00
George Kyriazis 0cd9ad98a3 swr/rast: AVX-512 changes to enable 16-wide VS
Add a new define (USE_SIMD16_VS), to denote calling a 16-wide vertex shader.
This is needed because the mesa driver can do 16-wide shaders, but rasty
cannot yet, so we need to distinguish.

Create a new VertexID entry (VertexID16) for the USE_SIMD16_VS case, since
we need to format the vertex id in a way that is digestible by the 16-wide VS

Disabled for now.  To be enabled in a future checkin when driver work
is complete.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:40 -06:00
George Kyriazis 3140e714d2 swr/rast: x86 autogenerated macro work
Add name argument to x86 autogenerated macros.
Add useful variable names for DCL_inputVec implementation.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:39 -06:00
George Kyriazis 4cd6e2ebfd swr/rast: Shorten some filenames
in shader and fetch dump files

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:39 -06:00
George Kyriazis 3936044d07 swr/rast: work supporting optimizations in Debug builds.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:38 -06:00
George Kyriazis c4a42f5add swr/rast: Add debugging type support for function types.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:38 -06:00
George Kyriazis e9e7f3ce0a swr/rast: Shader debugging work
- Move debug .ll files to JIT_CACHE_DIR
- Don't link against jitter SRGBLut table, add global data to shader that needs it.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:34 -06:00
George Kyriazis 34bbcb5052 swr/rast: Debug Symbols work
Added support for Fetch / Sample / LD functions
Added DLL link to JitCache implementation

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:30 -06:00
George Kyriazis 01ab218bbc swr/rast: Initial work for debugging support.
Adds ability to step into jitted llvm IR in Visual Studio.
- Updated llvm type generation script to also generate corresponding debug types.
- New module pass inserts debug metadata into the IR for each function

Disabled by default.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:22 -06:00
George Kyriazis 4660e13152 swr/rast: Add private state parameter in fetcher
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:48:41 -06:00
George Kyriazis 079ae3c48d swr/rast: Added missing define for Linux/gcc
+ ZeroMemory() macro definition for non win32-compilation in common/os.h

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:48:41 -06:00
George Kyriazis 70f8eac603 swr/rast: Fix one more invalid object format for windows.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:48:41 -06:00
Bas Nieuwenhuizen 61a790409e radv: Always re-emit the sample position offset user SGPR.
The user SGPR location can change between pipelines, so we need to
emit it again to the pottentially changed SGPR index.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 23:35:12 +01:00
Bas Nieuwenhuizen dbf1e918cd radv: emit pa_sc_mode_cntl_0 with multisample state.
We don't have the meta kludge with 0 viewports anymore,
so we can always enable them.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 23:35:12 +01:00
Kenneth Graunke c7dcee58b5 i965: Avoid problems from referencing orphaned BOs after growing.
Growing the batch/state buffer is a lot more dangerous than I thought.

A number of places emit multiple state buffer sections, and then write
data to the returned pointer, or save a pointer to brw->batch.state.bo
and then use it in relocations.  If each call can grow, this can result
in stale map references or stale BO pointers.  Furthermore, fences refer
to the old batch BO, and that reference needs to continue working.

To avoid these woes, we avoid ever swapping the brw->batch.*.bo pointer,
instead exchanging the brw_bo structures in place.  That way, stale BO
references are fine - the GEM handle changes, but the brw_bo pointer
doesn't.  We also defer the memcpy until a quiescent point, so callers
can write to the returned pointer - which may be in either BO - and
we'll sort it out and combine the two properly in the end.

v2/v3:
- Handle stale pointers in the shadow copy case, where realloc may or
  may not move our shadow copy to a new address.
- Track the partial map explicitly, to avoid problems with buffer reuse
  where multiple map modes exist (caught by Chris Wilson).

v4:
- Don't use realloc in the CPU shadow case, it isn't safe.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> [v3]
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2018-01-19 11:30:10 -08:00