Commit Graph

105854 Commits

Author SHA1 Message Date
Tapani Pälli 09adaa4b89 anv: allow exporting an imported SYNC_FD semaphore type
Fixes issues with following SkQP tests:

   unitTest_VulkanHardwareBuffer_Vulkan_EGL_Syncs
   unitTest_VulkanHardwareBuffer_Vulkan_Vulkan_Syncs

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-11-23 07:49:46 +02:00
Eric Engestrom 896c59d690 glapi: add missing visibility args
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108829
Fixes: 3218056e0e "meson: Build i965 and dri stack"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-22 18:21:05 +00:00
Jason Ekstrand a24654b49d anv/nir: Rework arguments to apply_pipeline_layout
Instead of taking a whole pipeline (which could be anything!), just take
a physical device and robust_buffer_access boolean.  This makes it
easier to verify that only the things in the hash actually affect
pipeline compilation.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-11-22 09:17:28 -06:00
Jason Ekstrand 617e402b3d anv: Put robust buffer access in the pipeline hash
It affects apply_pipeline_layout.  Shaders compiled with the wrong value
will work but they may not be robust as requested by the app.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-11-22 09:17:10 -06:00
Jason Ekstrand a845c2bc10 anv: Expose VK_EXT_scalar_block_layout
Our compile already splits UBO loads into scalars and the untyped
surface read messages we use for SSBO reads and writes only require
dword alignment.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-11-22 08:16:47 -06:00
Jason Ekstrand 2ca9a4417d vulkan: Update the XML and headers to 1.1.93
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-11-22 08:16:40 -06:00
Samuel Pitoiset 4ff4af3d91 radv: remove useless sync after CmdClear{Color,DepthStencil}Image()
'post_flush' is only set to NULL for the normal clear path
(ie. only vkCmdClearColorImage() and vkCmdClearDepthStencilImage()
are affected commands).

Because these two operations have to be externally synchronized
with VK_PIPELINE_STAGE_TRANSFER_BIT and VK_ACCESS_TRANSFER_WRITE_BIT,
it's useless to set those flags internallY.

VK_PIPELINE_STAGE_TRANSFER_BIT will wait for compute to be idle,
while VK_ACCESS_TRANSFER_WRITE_BIT will invalidate both L1 vector
caches and L2. RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 will be superseded
by RADV_CMD_FLAG_INV_GLOBAL_L2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-22 08:56:36 +01:00
Bas Nieuwenhuizen 33b2f74e77 vulkan: Allow storage images in the WSI.
Since apps also have to follow the ImageFormatProperties query,
we can disallow formats that don't allow image stores (for AMD
that would be SRGB formats).

Note that this only affects anything if the app actually decides
to use the flag.

Had someone ask for this on IRC and at least on the AMD side we
can support it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-11-21 21:36:55 +01:00
Axel Davy 1f1d4d571a st/nine: Remove thread_submit warning
thread_submit can be useful even without DRI_PRIME,
as it can help avoid missed pageflips.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2018-11-21 19:55:28 +01:00
Axel Davy d304f0aa31 st/nine: Allow 'triple buffering' with thread_submit
The path allowing triple buffering behaviour wasn't implemented
yet for thread_submit

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2018-11-21 19:55:28 +01:00
Robert Foss 19af208c7d
virgl: add assert and missing function parameter
Verify the pipe_fd_type to be of PIPE_FD_TYPE_NATIVE_SYNC.

Fixes: d1a1c21e76 "virgl: native fence fd support"

Suggested-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-21 15:59:00 +01:00
Gert Wollny 61b535437e r600: clean up the GS ring buffers when the context is destroyed
This fixes two memory leaks reported by ASAN:

Direct leak of 248 byte(s) in 1 object(s) allocated from:
   in malloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdb880)
   in r600_alloc_buffer_struct ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:578
   in r600_buffer_create ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:600
   in r600_resource_create_common ../../samba/mesa/src/gallium/drivers/r600/r600_pipe_common.c:1265
   in r600_resource_create ../../samba/mesa/src/gallium/drivers/r600/r600_pipe.c:725
   in pipe_buffer_create ../../samba/mesa/src/gallium/auxiliary/util/u_inlines.h:291
   in update_gs_block_state ../../samba/mesa/src/gallium/drivers/r600/r600_state_common.c:1482

Direct leak of 248 byte(s) in 1 object(s) allocated from:
   in malloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdb880)
   in r600_alloc_buffer_struct ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:578
   in r600_buffer_create ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:600
   in r600_resource_create_common ../../samba/mesa/src/gallium/drivers/r600/r600_pipe_common.c:1265
   in r600_resource_create ../../samba/mesa/src/gallium/drivers/r600/r600_pipe.c:722
   in pipe_buffer_create ../../samba/mesa/src/gallium/auxiliary/util/u_inlines.h:291
   in update_gs_block_state ../../samba/mesa/src/gallium/drivers/r600/r600_state_common.c:1489

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Fixes: 1371d65a7f
  r600g: initial support for geometry shaders on evergreen (v2)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-11-21 10:34:17 +01:00
Samuel Pitoiset 4b9bc4791b radv: only sync CP DMA for transfer operations or bottom pipe
CP DMA can only be busy when the driver copies buffers. The
only affected Vulkan commands are vkCmdCopyBuffer() and
vkCmdUpdateBuffer() (because we fallback to a copy depending on
a threshold). Clear operations are currently not concerned
because the driver always syncs after the last DMA operation.

Per the spec, these two operations have to be externally
synchronized with VK_PIPELINE_STAGE_TRANSFER_BIT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-21 10:03:01 +01:00
Samuel Pitoiset 457ac6ce1e radv: ignore subpass self-dependencies
Unnecessary as they allow the app to call vkCmdPipelineBarrier()
inside the render pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-21 10:02:59 +01:00
Iago Toral Quiroga 8e73b57634 Revert "nir/builder: Assert that intN_t immediates fit"
This reverts commit 1f29f4db1e.

For this to work the compiler must ensure that it never puts
the values that arrive to this helper into unsigned variables
at any point in its processing, since that would not apply sign
extension to the value and it would break the expectations here.
Unfortunately, we use uint64_t extensively to pass and copy
things around, so some times we get to this helper with values
that are not properly sign extended to 64-bit. Here is an example
for an 8-bit value that comes from a switch case:

(gdb) p /x x
$1 = 0xffffffd6

The value seems to have been sign extended to 32-bit at some point
getting proper sign extension, but then copied into a uint64_t
which wont' apply sign extension, breaking the expectations of
the assertion.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-11-21 08:12:50 +01:00
Iago Toral Quiroga 387888e3b7 nir/from_ssa: fix bit-size of temporary register
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-11-21 08:07:22 +01:00
Mathias Fröhlich 2d3c466add mesa: Remove unneeded bitfield widths from the VAO.
With the current VAO layout we do not need to make these
fields a bitfield. We get a tight struct layout with this change
for VAO attributes.

v2: Change unsigned char -> GLubyte.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-11-21 06:27:19 +01:00
Mathias Fröhlich 0a7020b4e6 mesa: Factor out struct gl_vertex_format.
Factor out struct gl_vertex_format from array attributes.
The data type is supposed to describe the type of a vertex
element. At this current stage the data type is only used
with the VAO, but actually is useful in various other places.
Due to the bitfields being used, special care needs to be
taken for the glGet code paths.

v2: Change unsigned char -> GLubyte.
    Use struct assignment for struct gl_vertex_format.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-11-21 06:27:19 +01:00
Mathias Fröhlich 2da7b0a2fb tnl: Use gl_array_attribute::_ElementSize.
Instead of open coding the size computation, use the
already available gl_array_attribute::_ElementSize value.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-11-21 06:27:19 +01:00
Mathias Fröhlich a4c01839c2 nouveau: Use gl_array_attribute::_ElementSize.
Instead of open coding the size computation, use the
already available gl_array_attribute::_ElementSize value.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-11-21 06:27:19 +01:00
Mathias Fröhlich 182ed6de8c mesa: Unify glEdgeFlagPointer data type.
Use GL_UNSIGNED_BYTE as initialization data type
for the edge flag vertex attribute array. The same datatype
is used in the glEdgeFlagPointer function when setting the
array pointer.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-11-21 06:27:19 +01:00
Mathias Fröhlich 1b743e2966 mesa: Work with bitmasks when en/dis-abling VAO arrays.
For enabling or disabling VAO arrays it is now possible to
change a set of arrays with a single call without the need to
iterate the attributes.
Make use of this technique in the vao module.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-11-21 06:27:19 +01:00
Mathias Fröhlich 3c46fa5988 mesa: Remove gl_array_attributes::Enabled.
Now that all users go via the VAO Enabled bitfield,
get rid of the Enabled boolean.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-11-21 06:27:19 +01:00
Mathias Fröhlich 093aeb3565 mesa: Use gl_vertex_array_object::Enabled for glGet.
Instead of using gl_array_attributes::Enabled use the
much more compact representation stored in
gl_vertex_array_object::Enabled using the corresponding bits.
Keep the glGet changes in a seperate patch at least for review.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-11-21 06:27:19 +01:00
Mathias Fröhlich 1217a8448c mesa: Use the gl_vertex_array_object::Enabled bitfield.
Instead of using gl_array_attributes::Enabled use the
much more compact representation stored in
gl_vertex_array_object::Enabled using the corresponding bits.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-11-21 06:27:19 +01:00
Mathias Fröhlich 73d2d313e9 mesa: Rename gl_vertex_array_object::_Enabled -> Enabled.
Mark the up to now derived bitfield value now as primary
value by removing the underscore.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-11-21 06:27:19 +01:00
Marek Olšák ea9f95e2a6 radeonsi: go back to using bottom-of-pipe for beginning of TIME_ELAPSED
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102597

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-20 21:18:48 -05:00
Marek Olšák 6c1a34d2e7 radeonsi: don't send data after write-confirm with BOTTOM_OF_PIPE_TS
There are no writes.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-20 21:18:46 -05:00
Marek Olšák bc5adc27b5 st/mesa: pin driver threads to a fixed CCX when glthread is enabled
radeonsi has 3 driver threads (glthread, gallium, winsys), other drivers
may have 2 (glthread, gallium), so it makes sense to pin them to a random
CCX and keep that irrespective of the app thread.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-20 21:18:43 -05:00
Marek Olšák 48f2160936 st/mesa: regularly re-pin driver threads to the CCX where the app thread is
This is used when glthread is disabled.

Mesa pretty much chases the app thread on the CPU.
The performance is the same as pinning the app thread.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-20 21:18:30 -05:00
Marek Olšák ce7f84eb77 drirc: enable glthread for Talos Principle
Ryzen 1700X, Vega 56, 1600x900, 4xAA: improvement +4.4%

Immediate mode was needed.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-11-20 21:17:42 -05:00
Marek Olšák 7f1cac7ba6 mesa/glthread: enable immediate mode
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-11-20 21:17:41 -05:00
Marek Olšák 247d5a8e94 mesa/glthread: pass the function name to _mesa_glthread_restore_dispatch
If you insert printf there, you'll know why glthread was disabled.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-11-20 21:17:38 -05:00
Marek Olšák 25d95ed535 gallium/u_tests: fix MSVC build by using old-style zero initializers 2018-11-20 19:06:40 -05:00
Kenneth Graunke 562448b75a i965: Do NIR shader cloning in the caller.
This moves nir_shader_clone() to the driver-specific compile function,
rather than the shared src/intel/compiler code.  This allows i965 to do
key-specific passes before calling brw_compile_*.  Vulkan should not
need this cloning as it doesn't compile multiple variants.

We do need to continue cloning in the compute shader code because we
lower various things in NIR based on the SIMD width.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2018-11-20 15:53:46 -08:00
Kenneth Graunke 6a10dd08f4 i965: Use a 'nir' temporary rather than poking at brw_program
It's shorter and will also be useful when I adjust cloning soon.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2018-11-20 15:53:46 -08:00
Marek Olšák 0d17b685b1 gallium/u_tests: add a compute shader test that clears an image 2018-11-20 18:50:48 -05:00
Dave Airlie 3486fe655a ac: handle cast derefs
Just give back the same value for now.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-21 08:54:46 +10:00
Dave Airlie baa4bdd3a6 radv: handle loading from shared pointers
We won't have a var to load from, so don't try to the processing
required if we don't need it.

This avoids crashes in:
dEQP-VK.spirv_assembly.instruction.compute.variable_pointers.compute.workgroup_two_buffers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-21 08:54:42 +10:00
Dave Airlie ec9fe8abc7 ac: avoid casting pointers on bcsel and stores
For variable pointers we really don't want to case the pointers to int
without a good reason, just add a wrapper for bcsel loading and result
storing.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-21 08:54:25 +10:00
Dylan Baker a999798daa meson: Add tests to suites
Meson test has a concepts of suites, which allow tests to be grouped
together. This allows for a subtest of tests to be run only (say only
the tests for nir). A test can be added to more than one suite, but for
the most part I've only added a test to a single suite, though I've
added a compiler group that includes nir, glsl, and glcpp tests.

To use this you'll need to invoke meson test directly, instead of ninja
test (which always runs all targets). it can be invoked as:
`meson test -C builddir --suite $suitename` (meson test has addition
options that are pretty useful).

Tested-By: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-20 09:09:22 -08:00
Andrii Simiklit b787dcf57b
i965/batch: avoid reverting batch buffer if saved state is an empty
There's no point reverting to the last saved point if that save point is
the empty batch, we will just repeat ourselves.

v2: Merge with new commits, changes was minimized, added the 'fixes' tag
v3: Added in to patch series
v4: Fixed the regression which was introduced by this patch
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108630
    Reported-by:  Mark Janes <mark.a.janes@intel.com>
    The solution provided by: Jordan Justen <jordan.l.justen@intel.com>

CC: Chris Wilson <chris@chris-wilson.co.uk>
Fixes: 3faf56ffbd "intel: Add an interface for saving/restoring
                     the batchbuffer state."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107626
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108630 (fixed in v4)
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-11-20 06:33:43 -08:00
Emil Velikov 982e012b3a travis: adding missing x11-xcb for meson+vulkan
Required by the x11 WSI

Fixes: df82012b2c ("travis: add meson build for vulkan drivers.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-11-20 11:16:46 +00:00
Emil Velikov 5bc509363b glx: make xf86vidmode mandatory for direct rendering
Currently we detect the module and if missing, the glXGetMsc* API is
effectively a stub, always returning false.

This is what effectively has been happening with our meson build :-(

Thus users have no chance of using it - they cannot even distinguish
if the failure is due to a misconfigured build.

There's no reason for keeping xf86vidmode optional - it has been
available in all distributions for years.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes: a47c525f32 "meson: build glx"
2018-11-20 11:13:20 +00:00
Emil Velikov 84445a86d1 travis: drop unneeded x11proto-xf86vidmode-dev
The only place where the package is needed is for building the DRI
based libGL library.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-20 11:13:20 +00:00
Samuel Pitoiset f4563d8f5b ac/nir: fix intrinsic name string size in visit_image_atomic()
Fixes an assertion in SoTTR.

Fixes: dd0172e865 ("radv: Use structured intrinsics instead of indexing workaround for GFX9.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-20 10:23:45 +01:00
Bas Nieuwenhuizen dd0172e865 radv: Use structured intrinsics instead of indexing workaround for GFX9.
These force the index to be used in the instruction so we don't need the
workaround.

Totals:
SGPRS: 1321642 -> 1321802 (0.01 %)
VGPRS: 943664 -> 943788 (0.01 %)
Spilled SGPRs: 28468 -> 28480 (0.04 %)
Spilled VGPRs: 88 -> 89 (1.14 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 80 -> 80 (0.00 %) dwords per thread
Code Size: 52415292 -> 52338932 (-0.15 %) bytes
LDS: 400 -> 400 (0.00 %) blocks
Max Waves: 233903 -> 233803 (-0.04 %)
Wait states: 0 -> 0 (0.00 %)

Totals from affected shaders:
SGPRS: 238344 -> 238504 (0.07 %)
VGPRS: 232732 -> 232856 (0.05 %)
Spilled SGPRs: 13125 -> 13137 (0.09 %)
Spilled VGPRs: 88 -> 89 (1.14 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 80 -> 80 (0.00 %) dwords per thread
Code Size: 15752712 -> 15676352 (-0.48 %) bytes
LDS: 139 -> 139 (0.00 %) blocks
Max Waves: 31680 -> 31580 (-0.32 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-11-19 23:36:00 +01:00
Kenneth Graunke 0990168642 i965: Allow only one slot of clip distances to be set on Gen4-5.
The existing backend code assumed that if VARYING_SLOT_CLIP_DIST0
was written, then VARYING_SLOT_CLIP_DIST1 would be as well.  That's
true with the current lowering, but not necessary if there are 4 or
fewer clip distances.  Separate out the checks to allow this.

The new NIR-based lowering will trigger this case, which would have
caused backend validation errors (src is null) without this patch.

Reviewed-by: Eric Anholt <eric@anholt.net>
2018-11-19 14:33:16 -08:00
Kenneth Graunke 5b682143da nir: Make nir_lower_clip_vs optionally work with variables.
The way nir_lower_clip_vs() works with store_output intrinsics makes a
ton of assumptions about the driver_location field.

In i965 and iris, I'd rather do this lowering early and work with
variables.  v3d may want to switch to that as well, and ir3 could too,
but I'm not sure exactly what would need updating.  For now, handle
both methods.

Reviewed-by: Eric Anholt <eric@anholt.net>
2018-11-19 14:33:16 -08:00
Kenneth Graunke d0f746b645 nir: Save nir_variable pointers in nir_lower_clip_vs rather than locs.
I'll want the variables in the next patch.

Reviewed-by: Eric Anholt <eric@anholt.net>
2018-11-19 14:33:16 -08:00