Commit Graph

51534 Commits

Author SHA1 Message Date
Kenneth Graunke 532e99cbf2 glcpp: Add built-in #define for GL_ARB_uniform_buffer_object.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-07-09 11:11:59 -07:00
Vincent Lejeune 7fabb2b593 glsl: Parser handles "#extension GL_ARB_uniform_buffer_object"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-09 11:11:38 -07:00
Eric Anholt f4fb6bf088 glsl: Reduce a bit of extra code in the merging of layout qualifiers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-09 11:05:33 -07:00
Eric Anholt 60a784d56e glsl: Take advantage of the layout qualifier flags union to clean up parsing.
The got_one variable was set iff one of the bits in flags.i was set.

v2: Fix incorrect dropping of the ARB_conservative_depth warning.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-09 11:04:45 -07:00
Tom Stellard 9b00edc79a r600g: Don't create a texture for the memory_pool during screen init
This fixes a segfault in r600_screen_create() introduced by
eb065f5d9d

Reported by tilman on irc.
2012-07-09 12:14:07 -04:00
Tom Stellard 76b44034b9 radeon/llvm: Rename namespace from AMDIL to AMDGPU 2012-07-09 13:43:11 +00:00
Tom Stellard 39323e8f79 r600g: Update number of gprs when adding a vertex instruction 2012-07-09 13:42:24 +00:00
Tom Stellard da9c8a73ec r600g/compute: Use evergreen_cb() for binding RATs 2012-07-09 13:41:18 +00:00
Tom Stellard 960906d16b r600g: Add support for RATs in evergreen_cb() 2012-07-09 13:41:18 +00:00
Tom Stellard eb065f5d9d r600g: Use a texture as the underlying resource for compute_memory_pool
This the first step towards being able to use evergreen_cb to bind RATs.
2012-07-09 13:41:18 +00:00
Tom Stellard 9d36441374 r600g: Add is_rat flag to r600_resource_texture 2012-07-09 13:41:18 +00:00
Tom Stellard 3d3194e93c r600g: Add r600_context_pipe_state_emit()
This function is used when dispatching compute shader in order to avoid
mixing compute and 3D registers in the context's dirty list.  This
allows the compute code to resuse 3D functions like evergreen_cb, which
return a struct r600_pipe_state and still have control over when and how
the register writes are emitted.
2012-07-09 13:41:17 +00:00
Tom Stellard e00e1586dd r600g: Add pkt_flag parameter to r600_context_block_emit_dirty()
This allows the shader type bit to be set in the pm4 header when
emitting registers for compute shaders.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-07-09 13:41:17 +00:00
Tom Stellard 25145de03e r600g/compute: Move LOOP_CONST initialization to start_compute_cs atom 2012-07-09 13:41:17 +00:00
Tom Stellard 5016fe2d47 r600g: Add start_compute_cs atom to struct r600_context
The start_compute_cs atom initializes some config and context registers
to the values needed for running compute shaders.  When a compute shader
is dispatched, this atom is emitted after the start_cs_cmd atom, which
initializes registers that are common to both 3D and compute.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-07-09 13:41:17 +00:00
Tom Stellard 38be0966c7 r600g: Add pkt_flag member to struct r600_command_buffer
Some packets require the shader type bit (bit 1) to be set when
used for compute shaders.  The pkt_flag will be initialized to
RADEON_CP_PACKET3_COMPUTE_MODE for any struct r600_command_buffer used
for dispatching compute shaders and it will be or'd against the result of
the PKT3 macro when adding a new packet to a struct r600_command buffer.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-07-09 13:41:17 +00:00
Tom Stellard 7d0c17fe74 r600g: Only emit start_cs_cmd atom once for compute command streams 2012-07-09 13:41:17 +00:00
Marek Olšák 0a21b561c7 r600g: fix stencil texturing with Z32_FLOAT_S8X24_UINT 2012-07-09 13:58:00 +02:00
Marek Olšák a460df9299 r600g: add assertions after translate_colorswap/colorformat/dbformat/texformat 2012-07-09 13:57:59 +02:00
Marek Olšák c1e8c845ea r600g: inline r600_hw_copy_region 2012-07-09 13:57:59 +02:00
Marek Olšák 9974e9ac5d r600g: enable dual src blending on r7xx
No lockups here.
2012-07-09 13:57:59 +02:00
Marek Olšák 6657a7af61 r600g: use depth format from pipe_surface, not pipe_resource 2012-07-09 13:57:59 +02:00
Marek Olšák b278aba423 r600g: use u_box_origin_2d helper function 2012-07-09 13:57:59 +02:00
Marek Olšák 1f50f463eb gallium/u_blitter: consolidate some state changes 2012-07-09 13:57:59 +02:00
Marek Olšák 22d032707e r600g: remove stray semicolon 2012-07-07 15:09:57 +02:00
Marek Olšák 461e9f99c7 docs: document ARB_blend_func_extended and EXT_texture_rg in relnotes-8.1
also sort the extensions
2012-07-07 15:09:57 +02:00
Eric Anholt 1e28f55ab7 i965/fs: Invalidate live intervals after copy propagation.
For copy propgation, we've dropped the use of a GRF in favor of a
(probably later) use of a different GRF.  This definitely requires
invalidating intervals.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-06 14:20:33 -07:00
Eric Anholt 2343fe9a5d i965/fs: Invalidate live intervals in passes that remove an instruction.
Since live intervals are based on ip, removing an instruction trashes
the intervals unless we were to go do some surgery.  These happen to
usually remove a use of a grf, so it's time to recalculate, anyway.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
NOTE: This is a candidate for the 8.0 release branch.
2012-07-06 14:20:33 -07:00
Eric Anholt 25ca9cc823 i965/vs: Move the other two src_reg/dst_reg constructors to brw_vec4.cpp.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-06 14:20:33 -07:00
Eric Anholt b2f5d4c3ec i965/vs: Move class functions to brw_vec4.cpp.
This has less impact than for the FS (4k savings), because it was partially
done already, but makes things more consistent.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-06 14:20:32 -07:00
Eric Anholt fe27916ddf i965/fs: Move class functions from the header to .cpp files.
Cuts compile time for brw_fs.h changes from 2.7s to .7s and reduces
i965_dri.so size by 70k.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-06 14:20:32 -07:00
José Fonseca 8b1f1900d1 galahad: Check that texture format is supported. 2012-07-06 20:38:41 +01:00
José Fonseca ff8ddf399a galahad: More detailed resource checks. 2012-07-06 20:22:29 +01:00
José Fonseca f8e13e6d69 galahad: Fix zealous warnings. 2012-07-06 20:12:56 +01:00
José Fonseca 7bd926af89 galahad: Enumerate all methods that are missing. 2012-07-06 19:13:44 +01:00
José Fonseca 3d2550be9c galahad: Implement render_condition. 2012-07-06 18:45:14 +01:00
José Fonseca 5b45775e41 galahad: Don't implement context methods that are not implemented by the underlying pipe driver. 2012-07-06 18:38:51 +01:00
José Fonseca 3cb994afca galahad: Use debug_printf.
stderr is not visible on windows.
2012-07-06 18:38:39 +01:00
José Fonseca 1abb070633 galahad: Silence creation messages.
Let galahad warnings be true warnings.
2012-07-06 18:37:48 +01:00
José Fonseca d78dee1671 galahad: Use reference counting when destroying the wraped objects.
As the wrapped pipe driver may hold internal references.
2012-07-06 18:35:44 +01:00
José Fonseca fe602da63f galahad: Point to the galahad objects from the galahad sampler view.
And not the wraped driver's objects.
2012-07-06 18:35:32 +01:00
José Fonseca 04d29afb8b galahad: Don't defer index buffer when it's NULL. 2012-07-06 17:02:39 +01:00
José Fonseca 232073b0d9 target-helpers: Enable debug helpers only on debug builds.
Some of these helpers use debug_get_option, which works also on releases.
2012-07-06 15:05:16 +01:00
Marek Olšák c445b0f76d st/mesa: only expose ARB_shader_bit_encoding with GLSL 1.3
I don't think it's possible or even useful to use the extension with GLSL 1.2.

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-07-06 00:45:38 +02:00
Kristian Høgsberg 5f5746a692 egl_dri2: Reorganize the EGLImage constructors to share more code
We factor out all the EGL book-keeping into dri2_create_image() and
simplify the wayland case by using dupImage.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2012-07-05 14:22:07 -04:00
Kristian Høgsberg 1bb15c0a08 intel: Share common __DRIimage allocation code
We have the same switch and allocation code in two places.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-05 14:22:07 -04:00
Kristian Høgsberg 454fc07dde intel: Just look up image->internal_format using _mesa_get_format_base_format
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-05 14:22:07 -04:00
Kristian Høgsberg e408c17767 intel: Remove unused __DRIimage::data_type field
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-05 14:22:06 -04:00
Brian Paul bbe92dc608 svga: whitespace fixes 2012-07-05 08:07:26 -06:00
Brian Paul 76a6801240 Revert "mesa: #define fprintf to be __mingw_fprintf() on Mingw32"
This reverts commit cbffaf20e9.

Use the PRIx64 macro in the fprintf() call instead, as suggested
by Dylan Noblesmith.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-07-05 08:07:26 -06:00