radv: Don't enable DCC / TC compat HTILE for storage images.
We don't get a layout when binding to a descriptor set, but can assume that the LAYOUT is GENERAL. For DCC stores with the DCC bits set will result in a hang, so better be safe than sorry. Reviewed-by: Dave Airlie <airlied@redhat.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
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@ -240,7 +240,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
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const struct legacy_surf_level *base_level_info,
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unsigned base_level, unsigned first_level,
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unsigned block_width, bool is_stencil,
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uint32_t *state)
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bool is_storage_image, uint32_t *state)
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{
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uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
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uint64_t va = gpu_address;
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@ -264,11 +264,12 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
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if (chip_class >= VI) {
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state[6] &= C_008F28_COMPRESSION_EN;
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state[7] = 0;
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if (radv_vi_dcc_enabled(image, first_level)) {
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if (!is_storage_image && radv_vi_dcc_enabled(image, first_level)) {
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meta_va = gpu_address + image->dcc_offset;
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if (chip_class <= VI)
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meta_va += base_level_info->dcc_offset;
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} else if(image->tc_compatible_htile && image->surface.htile_size) {
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} else if(!is_storage_image && image->tc_compatible_htile &&
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image->surface.htile_size) {
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meta_va = gpu_address + image->htile_offset;
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}
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@ -600,7 +601,7 @@ radv_query_opaque_metadata(struct radv_device *device,
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desc, NULL);
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si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
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image->surface.blk_w, false, desc);
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image->surface.blk_w, false, false, desc);
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/* Clear the base address and set the relative DCC offset. */
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desc[0] = 0;
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@ -1013,7 +1014,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
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base_level_info,
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iview->base_mip,
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iview->base_mip,
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blk_w, is_stencil, descriptor);
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blk_w, is_stencil, is_storage_image, descriptor);
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}
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void
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