ilo: replace domains by reloc flags
It is simpler and is supported by the kernel. It cannot be used with libdrm_intel yet though.
This commit is contained in:
parent
01887593a4
commit
fbb869c1aa
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@ -746,7 +746,7 @@ upload_shaders(struct ilo_3d *hw3d, struct ilo_shader_cache *shc)
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intel_bo_unreference(hw3d->kernel.bo);
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hw3d->kernel.bo = intel_winsys_alloc_buffer(hw3d->cp->winsys,
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"kernel bo", new_size, INTEL_DOMAIN_CPU);
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"kernel bo", new_size, true);
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if (!hw3d->kernel.bo) {
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ilo_err("failed to allocate kernel bo\n");
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return false;
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@ -95,7 +95,7 @@ ilo_3d_pipeline_create(struct ilo_cp *cp, const struct ilo_dev_info *dev)
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p->invalidate_flags = ILO_3D_PIPELINE_INVALIDATE_ALL;
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p->workaround_bo = intel_winsys_alloc_buffer(p->cp->winsys,
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"PIPE_CONTROL workaround", 4096, INTEL_DOMAIN_INSTRUCTION);
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"PIPE_CONTROL workaround", 4096, false);
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if (!p->workaround_bo) {
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ilo_warn("failed to allocate PIPE_CONTROL workaround bo\n");
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FREE(p);
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@ -153,8 +153,7 @@ gen6_emit_COLOR_BLT(struct ilo_dev_info *dev,
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ilo_cp_write(cp, dw0);
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ilo_cp_write(cp, dw1);
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ilo_cp_write(cp, height << 16 | width);
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ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
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INTEL_DOMAIN_RENDER);
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ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
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ilo_cp_write(cp, pattern);
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ilo_cp_end(cp);
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}
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@ -204,8 +203,7 @@ gen6_emit_XY_COLOR_BLT(struct ilo_dev_info *dev,
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ilo_cp_write(cp, dw1);
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ilo_cp_write(cp, y1 << 16 | x1);
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ilo_cp_write(cp, y2 << 16 | x2);
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ilo_cp_write_bo(cp, dst_offset, dst_bo,
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INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
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ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
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ilo_cp_write(cp, pattern);
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ilo_cp_end(cp);
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}
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@ -247,10 +245,9 @@ gen6_emit_SRC_COPY_BLT(struct ilo_dev_info *dev,
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ilo_cp_write(cp, dw0);
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ilo_cp_write(cp, dw1);
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ilo_cp_write(cp, height << 16 | width);
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ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
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INTEL_DOMAIN_RENDER);
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ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
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ilo_cp_write(cp, src_pitch);
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ilo_cp_write_bo(cp, src_offset, src_bo, INTEL_DOMAIN_RENDER, 0);
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ilo_cp_write_bo(cp, src_offset, src_bo, 0);
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ilo_cp_end(cp);
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}
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@ -316,11 +313,10 @@ gen6_emit_XY_SRC_COPY_BLT(struct ilo_dev_info *dev,
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ilo_cp_write(cp, dw1);
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ilo_cp_write(cp, y1 << 16 | x1);
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ilo_cp_write(cp, y2 << 16 | x2);
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ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
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INTEL_DOMAIN_RENDER);
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ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
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ilo_cp_write(cp, src_y << 16 | src_x);
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ilo_cp_write(cp, src_pitch >> src_pitch_shift);
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ilo_cp_write_bo(cp, src_offset, src_bo, INTEL_DOMAIN_RENDER, 0);
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ilo_cp_write_bo(cp, src_offset, src_bo, 0);
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ilo_cp_end(cp);
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}
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@ -163,7 +163,7 @@ ilo_cp_realloc_bo(struct ilo_cp *cp)
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* won't point at the same address, which is needed for jmpbuf
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*/
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bo = intel_winsys_alloc_buffer(cp->winsys,
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"batch buffer", cp->bo_size * 4, INTEL_DOMAIN_CPU);
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"batch buffer", cp->bo_size * 4, true);
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if (unlikely(!bo)) {
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/* reuse the old one */
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bo = cp->bo;
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@ -320,14 +320,14 @@ ilo_cp_write_multi(struct ilo_cp *cp, const void *vals, int num_vals)
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* bo to the buffer, it also emits a relocation.
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*/
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static inline void
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ilo_cp_write_bo(struct ilo_cp *cp, uint32_t val, struct intel_bo *bo,
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uint32_t read_domains, uint32_t write_domain)
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ilo_cp_write_bo(struct ilo_cp *cp, uint32_t val,
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struct intel_bo *bo, uint32_t flags)
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{
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uint64_t presumed_offset;
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if (bo) {
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intel_bo_add_reloc(cp->bo, cp->cmd_cur * 4, bo, val,
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read_domains, write_domain, &presumed_offset);
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intel_bo_add_reloc(cp->bo, cp->cmd_cur * 4, bo, val, flags,
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&presumed_offset);
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}
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else {
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presumed_offset = 0;
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@ -253,8 +253,6 @@ gen6_emit_MI_STORE_DATA_IMM(const struct ilo_dev_info *dev,
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const uint8_t cmd_len = (store_qword) ? 5 : 4;
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/* must use GGTT on GEN6 as in PIPE_CONTROL */
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const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
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const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
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const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
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ILO_GPE_VALID_GEN(dev, 6, 7.5);
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@ -263,7 +261,7 @@ gen6_emit_MI_STORE_DATA_IMM(const struct ilo_dev_info *dev,
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ilo_cp_begin(cp, cmd_len);
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ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
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ilo_cp_write(cp, 0);
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ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
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ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
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ilo_cp_write(cp, (uint32_t) val);
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if (store_qword)
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@ -302,8 +300,6 @@ gen6_emit_MI_STORE_REGISTER_MEM(const struct ilo_dev_info *dev,
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const uint8_t cmd_len = 3;
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/* must use GGTT on GEN6 as in PIPE_CONTROL */
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const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
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const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
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const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
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ILO_GPE_VALID_GEN(dev, 6, 7.5);
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@ -312,7 +308,7 @@ gen6_emit_MI_STORE_REGISTER_MEM(const struct ilo_dev_info *dev,
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ilo_cp_begin(cp, cmd_len);
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ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
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ilo_cp_write(cp, reg);
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ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
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ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
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ilo_cp_end(cp);
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}
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@ -323,8 +319,6 @@ gen6_emit_MI_REPORT_PERF_COUNT(const struct ilo_dev_info *dev,
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{
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const uint32_t cmd = ILO_GPE_MI(0x28);
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const uint8_t cmd_len = 3;
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const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
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const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
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ILO_GPE_VALID_GEN(dev, 6, 7.5);
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@ -336,7 +330,7 @@ gen6_emit_MI_REPORT_PERF_COUNT(const struct ilo_dev_info *dev,
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ilo_cp_begin(cp, cmd_len);
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ilo_cp_write(cp, cmd | (cmd_len - 2));
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ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
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ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
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ilo_cp_write(cp, report_id);
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ilo_cp_end(cp);
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}
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@ -366,26 +360,14 @@ gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
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ilo_cp_begin(cp, cmd_len);
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ilo_cp_write(cp, cmd | (cmd_len - 2));
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ilo_cp_write_bo(cp, 1, general_state_bo,
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INTEL_DOMAIN_RENDER,
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0);
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ilo_cp_write_bo(cp, 1, surface_state_bo,
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INTEL_DOMAIN_SAMPLER,
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0);
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ilo_cp_write_bo(cp, 1, dynamic_state_bo,
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INTEL_DOMAIN_RENDER | INTEL_DOMAIN_INSTRUCTION,
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0);
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ilo_cp_write_bo(cp, 1, indirect_object_bo,
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0,
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0);
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ilo_cp_write_bo(cp, 1, instruction_bo,
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INTEL_DOMAIN_INSTRUCTION,
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0);
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ilo_cp_write_bo(cp, 1, general_state_bo, 0);
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ilo_cp_write_bo(cp, 1, surface_state_bo, 0);
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ilo_cp_write_bo(cp, 1, dynamic_state_bo, 0);
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ilo_cp_write_bo(cp, 1, indirect_object_bo, 0);
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ilo_cp_write_bo(cp, 1, instruction_bo, 0);
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if (general_state_size) {
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ilo_cp_write_bo(cp, general_state_size | 1, general_state_bo,
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INTEL_DOMAIN_RENDER,
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0);
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ilo_cp_write_bo(cp, general_state_size | 1, general_state_bo, 0);
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}
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else {
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/* skip range check */
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@ -393,9 +375,7 @@ gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
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}
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if (dynamic_state_size) {
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ilo_cp_write_bo(cp, dynamic_state_size | 1, dynamic_state_bo,
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INTEL_DOMAIN_RENDER | INTEL_DOMAIN_INSTRUCTION,
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0);
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ilo_cp_write_bo(cp, dynamic_state_size | 1, dynamic_state_bo, 0);
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}
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else {
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/* skip range check */
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@ -403,9 +383,7 @@ gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
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}
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if (indirect_object_size) {
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ilo_cp_write_bo(cp, indirect_object_size | 1, indirect_object_bo,
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0,
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0);
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ilo_cp_write_bo(cp, indirect_object_size | 1, indirect_object_bo, 0);
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}
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else {
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/* skip range check */
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@ -413,9 +391,7 @@ gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
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}
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if (instruction_size) {
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ilo_cp_write_bo(cp, instruction_size | 1, instruction_bo,
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INTEL_DOMAIN_INSTRUCTION,
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0);
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ilo_cp_write_bo(cp, instruction_size | 1, instruction_bo, 0);
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}
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else {
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/* skip range check */
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@ -741,8 +717,8 @@ gen6_emit_3DSTATE_VERTEX_BUFFERS(const struct ilo_dev_info *dev,
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dw |= cso->stride << GEN6_VB_STATE_DW0_PITCH__SHIFT;
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ilo_cp_write(cp, dw);
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ilo_cp_write_bo(cp, start_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
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ilo_cp_write_bo(cp, end_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
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ilo_cp_write_bo(cp, start_offset, buf->bo, 0);
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ilo_cp_write_bo(cp, end_offset, buf->bo, 0);
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ilo_cp_write(cp, instance_divisor);
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}
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else {
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@ -951,8 +927,8 @@ gen6_emit_3DSTATE_INDEX_BUFFER(const struct ilo_dev_info *dev,
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ilo_cp_write(cp, cmd | (cmd_len - 2) |
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((enable_cut_index) ? GEN6_IB_DW0_CUT_INDEX_ENABLE : 0) |
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format);
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ilo_cp_write_bo(cp, start_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
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ilo_cp_write_bo(cp, end_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
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ilo_cp_write_bo(cp, start_offset, buf->bo, 0);
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ilo_cp_write_bo(cp, end_offset, buf->bo, 0);
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ilo_cp_end(cp);
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}
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@ -1527,8 +1503,7 @@ gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
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ilo_cp_begin(cp, cmd_len);
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ilo_cp_write(cp, cmd | (cmd_len - 2));
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ilo_cp_write(cp, zs->payload[0]);
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ilo_cp_write_bo(cp, zs->payload[1], zs->bo,
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INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
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ilo_cp_write_bo(cp, zs->payload[1], zs->bo, INTEL_RELOC_WRITE);
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ilo_cp_write(cp, zs->payload[2]);
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ilo_cp_write(cp, zs->payload[3]);
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ilo_cp_write(cp, zs->payload[4]);
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@ -1713,8 +1688,7 @@ gen6_emit_3DSTATE_STENCIL_BUFFER(const struct ilo_dev_info *dev,
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ilo_cp_write(cp, cmd | (cmd_len - 2));
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/* see ilo_gpe_init_zs_surface() */
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ilo_cp_write(cp, zs->payload[6]);
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ilo_cp_write_bo(cp, zs->payload[7], zs->separate_s8_bo,
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INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
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ilo_cp_write_bo(cp, zs->payload[7], zs->separate_s8_bo, INTEL_RELOC_WRITE);
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ilo_cp_end(cp);
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}
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@ -1734,8 +1708,7 @@ gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(const struct ilo_dev_info *dev,
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ilo_cp_write(cp, cmd | (cmd_len - 2));
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/* see ilo_gpe_init_zs_surface() */
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ilo_cp_write(cp, zs->payload[8]);
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ilo_cp_write_bo(cp, zs->payload[9], zs->hiz_bo,
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INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
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ilo_cp_write_bo(cp, zs->payload[9], zs->hiz_bo, INTEL_RELOC_WRITE);
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ilo_cp_end(cp);
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}
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@ -1765,8 +1738,6 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev,
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{
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const uint32_t cmd = ILO_GPE_CMD(0x3, 0x2, 0x00);
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const uint8_t cmd_len = (write_qword) ? 5 : 4;
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const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
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const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
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ILO_GPE_VALID_GEN(dev, 6, 7.5);
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@ -1839,7 +1810,7 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev,
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ilo_cp_begin(cp, cmd_len);
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ilo_cp_write(cp, cmd | (cmd_len - 2));
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ilo_cp_write(cp, dw1);
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ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
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ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
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ilo_cp_write(cp, 0);
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if (write_qword)
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ilo_cp_write(cp, 0);
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@ -2286,26 +2257,16 @@ gen6_emit_SURFACE_STATE(const struct ilo_dev_info *dev,
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const int state_align = 32 / 4;
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const int state_len = (dev->gen >= ILO_GEN(7)) ? 8 : 6;
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uint32_t state_offset;
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uint32_t read_domains, write_domain;
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ILO_GPE_VALID_GEN(dev, 6, 7.5);
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if (for_render) {
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read_domains = INTEL_DOMAIN_RENDER;
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write_domain = INTEL_DOMAIN_RENDER;
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}
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else {
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read_domains = INTEL_DOMAIN_SAMPLER;
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write_domain = 0;
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}
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ilo_cp_steal(cp, "SURFACE_STATE", state_len, state_align, &state_offset);
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STATIC_ASSERT(Elements(surf->payload) >= 8);
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ilo_cp_write(cp, surf->payload[0]);
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ilo_cp_write_bo(cp, surf->payload[1],
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surf->bo, read_domains, write_domain);
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ilo_cp_write_bo(cp, surf->payload[1], surf->bo,
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(for_render) ? INTEL_RELOC_WRITE : 0);
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ilo_cp_write(cp, surf->payload[2]);
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ilo_cp_write(cp, surf->payload[3]);
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ilo_cp_write(cp, surf->payload[4]);
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@ -1036,8 +1036,8 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
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ilo_cp_write(cp, cmd | (cmd_len - 2));
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ilo_cp_write(cp, index << GEN7_SO_BUF_DW1_INDEX__SHIFT |
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stride);
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ilo_cp_write_bo(cp, base, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
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ilo_cp_write_bo(cp, end, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
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ilo_cp_write_bo(cp, base, buf->bo, INTEL_RELOC_WRITE);
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ilo_cp_write_bo(cp, end, buf->bo, INTEL_RELOC_WRITE);
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ilo_cp_end(cp);
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}
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@ -229,7 +229,7 @@ ilo_query_alloc_bo(struct ilo_query *q, int reg_count, int repeat_count,
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intel_bo_unreference(q->bo);
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q->bo = intel_winsys_alloc_buffer(winsys,
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name, size, INTEL_DOMAIN_INSTRUCTION);
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name, size, false);
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q->reg_total = (q->bo) ? reg_total : 0;
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}
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@ -76,13 +76,12 @@ resource_get_bo_name(const struct pipe_resource *templ)
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return name;
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}
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static enum intel_domain_flag
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resource_get_bo_initial_domain(const struct pipe_resource *templ)
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static bool
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resource_get_cpu_init(const struct pipe_resource *templ)
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{
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return (templ->bind & (PIPE_BIND_DEPTH_STENCIL |
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PIPE_BIND_RENDER_TARGET |
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PIPE_BIND_STREAM_OUTPUT)) ?
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INTEL_DOMAIN_RENDER : 0;
|
||||
PIPE_BIND_STREAM_OUTPUT)) ? false : true;
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -152,11 +151,10 @@ tex_create_bo(struct ilo_texture *tex)
|
|||
{
|
||||
struct ilo_screen *is = ilo_screen(tex->base.screen);
|
||||
const char *name = resource_get_bo_name(&tex->base);
|
||||
const enum intel_domain_flag initial_domain =
|
||||
resource_get_bo_initial_domain(&tex->base);
|
||||
const bool cpu_init = resource_get_cpu_init(&tex->base);
|
||||
|
||||
tex->bo = intel_winsys_alloc_bo(is->winsys, name, tex->layout.tiling,
|
||||
tex->layout.bo_stride, tex->layout.bo_height, initial_domain);
|
||||
tex->layout.bo_stride, tex->layout.bo_height, cpu_init);
|
||||
|
||||
return (tex->bo != NULL);
|
||||
}
|
||||
|
@ -194,7 +192,7 @@ tex_create_hiz(struct ilo_texture *tex)
|
|||
|
||||
tex->aux_bo = intel_winsys_alloc_bo(is->winsys, "hiz texture",
|
||||
INTEL_TILING_Y, tex->layout.aux_stride, tex->layout.aux_height,
|
||||
INTEL_DOMAIN_RENDER);
|
||||
false);
|
||||
if (!tex->aux_bo)
|
||||
return false;
|
||||
|
||||
|
@ -224,7 +222,7 @@ tex_create_mcs(struct ilo_texture *tex)
|
|||
|
||||
tex->aux_bo = intel_winsys_alloc_bo(is->winsys, "mcs texture",
|
||||
INTEL_TILING_Y, tex->layout.aux_stride, tex->layout.aux_height,
|
||||
INTEL_DOMAIN_RENDER);
|
||||
false);
|
||||
if (!tex->aux_bo)
|
||||
return false;
|
||||
|
||||
|
@ -357,11 +355,10 @@ buf_create_bo(struct ilo_buffer *buf)
|
|||
{
|
||||
struct ilo_screen *is = ilo_screen(buf->base.screen);
|
||||
const char *name = resource_get_bo_name(&buf->base);
|
||||
const enum intel_domain_flag initial_domain =
|
||||
resource_get_bo_initial_domain(&buf->base);
|
||||
const bool cpu_init = resource_get_cpu_init(&buf->base);
|
||||
|
||||
buf->bo = intel_winsys_alloc_buffer(is->winsys, name,
|
||||
buf->bo_size, initial_domain);
|
||||
buf->bo_size, cpu_init);
|
||||
|
||||
return (buf->bo != NULL);
|
||||
}
|
||||
|
|
|
@ -195,12 +195,7 @@ intel_winsys_create_for_fd(int fd)
|
|||
|
||||
/*
|
||||
* No need to implicitly set up a fence register for each non-linear reloc
|
||||
* entry. When a fence register is needed for a reloc entry,
|
||||
* drm_intel_bo_emit_reloc_fence() will be called explicitly.
|
||||
*
|
||||
* intel_bo_add_reloc() currently lacks "bool fenced" for this to work.
|
||||
* But we never need a fence register on GEN4+ so we do not need to worry
|
||||
* about it yet.
|
||||
* entry. INTEL_RELOC_FENCE will be set on reloc entries that need them.
|
||||
*/
|
||||
drm_intel_bufmgr_gem_enable_fenced_relocs(winsys->bufmgr);
|
||||
|
||||
|
@ -266,10 +261,8 @@ intel_winsys_alloc_bo(struct intel_winsys *winsys,
|
|||
enum intel_tiling_mode tiling,
|
||||
unsigned long pitch,
|
||||
unsigned long height,
|
||||
uint32_t initial_domain)
|
||||
bool cpu_init)
|
||||
{
|
||||
const bool for_render =
|
||||
(initial_domain & (INTEL_DOMAIN_RENDER | INTEL_DOMAIN_INSTRUCTION));
|
||||
const unsigned int alignment = 4096; /* always page-aligned */
|
||||
unsigned long size;
|
||||
drm_intel_bo *bo;
|
||||
|
@ -292,12 +285,12 @@ intel_winsys_alloc_bo(struct intel_winsys *winsys,
|
|||
|
||||
size = pitch * height;
|
||||
|
||||
if (for_render) {
|
||||
bo = drm_intel_bo_alloc_for_render(winsys->bufmgr,
|
||||
name, size, alignment);
|
||||
if (cpu_init) {
|
||||
bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment);
|
||||
}
|
||||
else {
|
||||
bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment);
|
||||
bo = drm_intel_bo_alloc_for_render(winsys->bufmgr,
|
||||
name, size, alignment);
|
||||
}
|
||||
|
||||
if (bo && tiling != INTEL_TILING_NONE) {
|
||||
|
@ -558,14 +551,37 @@ intel_bo_pread(struct intel_bo *bo, unsigned long offset,
|
|||
int
|
||||
intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
|
||||
struct intel_bo *target_bo, uint32_t target_offset,
|
||||
uint32_t read_domains, uint32_t write_domain,
|
||||
uint64_t *presumed_offset)
|
||||
uint32_t flags, uint64_t *presumed_offset)
|
||||
{
|
||||
uint32_t read_domains, write_domain;
|
||||
int err;
|
||||
|
||||
err = drm_intel_bo_emit_reloc(gem_bo(bo), offset,
|
||||
gem_bo(target_bo), target_offset,
|
||||
read_domains, write_domain);
|
||||
if (flags & INTEL_RELOC_WRITE) {
|
||||
/*
|
||||
* Because of the translation to domains, INTEL_RELOC_GGTT should only
|
||||
* be set on GEN6 when the bo is written by MI_* or PIPE_CONTROL. The
|
||||
* kernel will translate it back to INTEL_RELOC_GGTT.
|
||||
*/
|
||||
write_domain = (flags & INTEL_RELOC_GGTT) ?
|
||||
I915_GEM_DOMAIN_INSTRUCTION : I915_GEM_DOMAIN_RENDER;
|
||||
read_domains = write_domain;
|
||||
} else {
|
||||
write_domain = 0;
|
||||
read_domains = I915_GEM_DOMAIN_RENDER |
|
||||
I915_GEM_DOMAIN_SAMPLER |
|
||||
I915_GEM_DOMAIN_INSTRUCTION |
|
||||
I915_GEM_DOMAIN_VERTEX;
|
||||
}
|
||||
|
||||
if (flags & INTEL_RELOC_FENCE) {
|
||||
err = drm_intel_bo_emit_reloc_fence(gem_bo(bo), offset,
|
||||
gem_bo(target_bo), target_offset,
|
||||
read_domains, write_domain);
|
||||
} else {
|
||||
err = drm_intel_bo_emit_reloc(gem_bo(bo), offset,
|
||||
gem_bo(target_bo), target_offset,
|
||||
read_domains, write_domain);
|
||||
}
|
||||
|
||||
*presumed_offset = gem_bo(target_bo)->offset64 + target_offset;
|
||||
|
||||
|
|
|
@ -44,14 +44,10 @@ enum intel_exec_flag {
|
|||
};
|
||||
|
||||
/* this is compatible with i915_drm.h's definitions */
|
||||
enum intel_domain_flag {
|
||||
INTEL_DOMAIN_CPU = 0x00000001,
|
||||
INTEL_DOMAIN_RENDER = 0x00000002,
|
||||
INTEL_DOMAIN_SAMPLER = 0x00000004,
|
||||
INTEL_DOMAIN_COMMAND = 0x00000008,
|
||||
INTEL_DOMAIN_INSTRUCTION = 0x00000010,
|
||||
INTEL_DOMAIN_VERTEX = 0x00000020,
|
||||
INTEL_DOMAIN_GTT = 0x00000040,
|
||||
enum intel_reloc_flag {
|
||||
INTEL_RELOC_FENCE = 1 << 0,
|
||||
INTEL_RELOC_GGTT = 1 << 1,
|
||||
INTEL_RELOC_WRITE = 1 << 2,
|
||||
};
|
||||
|
||||
/* this is compatible with i915_drm.h's definitions */
|
||||
|
@ -126,7 +122,7 @@ intel_winsys_read_reg(struct intel_winsys *winsys,
|
|||
* \param tiling Tiling mode.
|
||||
* \param pitch Pitch of the bo.
|
||||
* \param height Height of the bo.
|
||||
* \param initial_domain Initial (write) domain.
|
||||
* \param cpu_init Will be initialized by CPU.
|
||||
*/
|
||||
struct intel_bo *
|
||||
intel_winsys_alloc_bo(struct intel_winsys *winsys,
|
||||
|
@ -134,7 +130,7 @@ intel_winsys_alloc_bo(struct intel_winsys *winsys,
|
|||
enum intel_tiling_mode tiling,
|
||||
unsigned long pitch,
|
||||
unsigned long height,
|
||||
uint32_t initial_domain);
|
||||
bool cpu_init);
|
||||
|
||||
/**
|
||||
* Allocate a linear buffer object.
|
||||
|
@ -143,10 +139,10 @@ static inline struct intel_bo *
|
|||
intel_winsys_alloc_buffer(struct intel_winsys *winsys,
|
||||
const char *name,
|
||||
unsigned long size,
|
||||
uint32_t initial_domain)
|
||||
bool cpu_init)
|
||||
{
|
||||
return intel_winsys_alloc_bo(winsys, name,
|
||||
INTEL_TILING_NONE, size, 1, initial_domain);
|
||||
INTEL_TILING_NONE, size, 1, cpu_init);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -275,8 +271,7 @@ intel_bo_pread(struct intel_bo *bo, unsigned long offset,
|
|||
int
|
||||
intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
|
||||
struct intel_bo *target_bo, uint32_t target_offset,
|
||||
uint32_t read_domains, uint32_t write_domain,
|
||||
uint64_t *presumed_offset);
|
||||
uint32_t flags, uint64_t *presumed_offset);
|
||||
|
||||
/**
|
||||
* Return the current number of relocations.
|
||||
|
|
Loading…
Reference in New Issue