diff --git a/src/gallium/drivers/ilo/ilo_3d.c b/src/gallium/drivers/ilo/ilo_3d.c
index 90063761d16..48984ba006a 100644
--- a/src/gallium/drivers/ilo/ilo_3d.c
+++ b/src/gallium/drivers/ilo/ilo_3d.c
@@ -746,7 +746,7 @@ upload_shaders(struct ilo_3d *hw3d, struct ilo_shader_cache *shc)
          intel_bo_unreference(hw3d->kernel.bo);
 
       hw3d->kernel.bo = intel_winsys_alloc_buffer(hw3d->cp->winsys,
-            "kernel bo", new_size, INTEL_DOMAIN_CPU);
+            "kernel bo", new_size, true);
       if (!hw3d->kernel.bo) {
          ilo_err("failed to allocate kernel bo\n");
          return false;
diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline.c b/src/gallium/drivers/ilo/ilo_3d_pipeline.c
index 1f18bbbedfe..1152a7ffc3e 100644
--- a/src/gallium/drivers/ilo/ilo_3d_pipeline.c
+++ b/src/gallium/drivers/ilo/ilo_3d_pipeline.c
@@ -95,7 +95,7 @@ ilo_3d_pipeline_create(struct ilo_cp *cp, const struct ilo_dev_info *dev)
    p->invalidate_flags = ILO_3D_PIPELINE_INVALIDATE_ALL;
 
    p->workaround_bo = intel_winsys_alloc_buffer(p->cp->winsys,
-         "PIPE_CONTROL workaround", 4096, INTEL_DOMAIN_INSTRUCTION);
+         "PIPE_CONTROL workaround", 4096, false);
    if (!p->workaround_bo) {
       ilo_warn("failed to allocate PIPE_CONTROL workaround bo\n");
       FREE(p);
diff --git a/src/gallium/drivers/ilo/ilo_blitter_blt.c b/src/gallium/drivers/ilo/ilo_blitter_blt.c
index 1dd00af6c9c..5c2d2d49821 100644
--- a/src/gallium/drivers/ilo/ilo_blitter_blt.c
+++ b/src/gallium/drivers/ilo/ilo_blitter_blt.c
@@ -153,8 +153,7 @@ gen6_emit_COLOR_BLT(struct ilo_dev_info *dev,
    ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, dw1);
    ilo_cp_write(cp, height << 16 | width);
-   ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
-                                           INTEL_DOMAIN_RENDER);
+   ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
    ilo_cp_write(cp, pattern);
    ilo_cp_end(cp);
 }
@@ -204,8 +203,7 @@ gen6_emit_XY_COLOR_BLT(struct ilo_dev_info *dev,
    ilo_cp_write(cp, dw1);
    ilo_cp_write(cp, y1 << 16 | x1);
    ilo_cp_write(cp, y2 << 16 | x2);
-   ilo_cp_write_bo(cp, dst_offset, dst_bo,
-                   INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+   ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
    ilo_cp_write(cp, pattern);
    ilo_cp_end(cp);
 }
@@ -247,10 +245,9 @@ gen6_emit_SRC_COPY_BLT(struct ilo_dev_info *dev,
    ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, dw1);
    ilo_cp_write(cp, height << 16 | width);
-   ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
-                                           INTEL_DOMAIN_RENDER);
+   ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
    ilo_cp_write(cp, src_pitch);
-   ilo_cp_write_bo(cp, src_offset, src_bo, INTEL_DOMAIN_RENDER, 0);
+   ilo_cp_write_bo(cp, src_offset, src_bo, 0);
    ilo_cp_end(cp);
 }
 
@@ -316,11 +313,10 @@ gen6_emit_XY_SRC_COPY_BLT(struct ilo_dev_info *dev,
    ilo_cp_write(cp, dw1);
    ilo_cp_write(cp, y1 << 16 | x1);
    ilo_cp_write(cp, y2 << 16 | x2);
-   ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
-                                           INTEL_DOMAIN_RENDER);
+   ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
    ilo_cp_write(cp, src_y << 16 | src_x);
    ilo_cp_write(cp, src_pitch >> src_pitch_shift);
-   ilo_cp_write_bo(cp, src_offset, src_bo, INTEL_DOMAIN_RENDER, 0);
+   ilo_cp_write_bo(cp, src_offset, src_bo, 0);
    ilo_cp_end(cp);
 }
 
diff --git a/src/gallium/drivers/ilo/ilo_cp.c b/src/gallium/drivers/ilo/ilo_cp.c
index ec99e0fb02e..0b2bbfacf4c 100644
--- a/src/gallium/drivers/ilo/ilo_cp.c
+++ b/src/gallium/drivers/ilo/ilo_cp.c
@@ -163,7 +163,7 @@ ilo_cp_realloc_bo(struct ilo_cp *cp)
     * won't point at the same address, which is needed for jmpbuf
     */
    bo = intel_winsys_alloc_buffer(cp->winsys,
-         "batch buffer", cp->bo_size * 4, INTEL_DOMAIN_CPU);
+         "batch buffer", cp->bo_size * 4, true);
    if (unlikely(!bo)) {
       /* reuse the old one */
       bo = cp->bo;
diff --git a/src/gallium/drivers/ilo/ilo_cp.h b/src/gallium/drivers/ilo/ilo_cp.h
index 15b66040f6e..b4963022b00 100644
--- a/src/gallium/drivers/ilo/ilo_cp.h
+++ b/src/gallium/drivers/ilo/ilo_cp.h
@@ -320,14 +320,14 @@ ilo_cp_write_multi(struct ilo_cp *cp, const void *vals, int num_vals)
  * bo to the buffer, it also emits a relocation.
  */
 static inline void
-ilo_cp_write_bo(struct ilo_cp *cp, uint32_t val, struct intel_bo *bo,
-                uint32_t read_domains, uint32_t write_domain)
+ilo_cp_write_bo(struct ilo_cp *cp, uint32_t val,
+                struct intel_bo *bo, uint32_t flags)
 {
    uint64_t presumed_offset;
 
    if (bo) {
-      intel_bo_add_reloc(cp->bo, cp->cmd_cur * 4, bo, val,
-            read_domains, write_domain, &presumed_offset);
+      intel_bo_add_reloc(cp->bo, cp->cmd_cur * 4, bo, val, flags,
+            &presumed_offset);
    }
    else {
       presumed_offset = 0;
diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen6.h b/src/gallium/drivers/ilo/ilo_gpe_gen6.h
index 8e394ded95f..efd928d2ed9 100644
--- a/src/gallium/drivers/ilo/ilo_gpe_gen6.h
+++ b/src/gallium/drivers/ilo/ilo_gpe_gen6.h
@@ -253,8 +253,6 @@ gen6_emit_MI_STORE_DATA_IMM(const struct ilo_dev_info *dev,
    const uint8_t cmd_len = (store_qword) ? 5 : 4;
    /* must use GGTT on GEN6 as in PIPE_CONTROL */
    const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
-   const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
-   const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
@@ -263,7 +261,7 @@ gen6_emit_MI_STORE_DATA_IMM(const struct ilo_dev_info *dev,
    ilo_cp_begin(cp, cmd_len);
    ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
    ilo_cp_write(cp, 0);
-   ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
+   ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
    ilo_cp_write(cp, (uint32_t) val);
 
    if (store_qword)
@@ -302,8 +300,6 @@ gen6_emit_MI_STORE_REGISTER_MEM(const struct ilo_dev_info *dev,
    const uint8_t cmd_len = 3;
    /* must use GGTT on GEN6 as in PIPE_CONTROL */
    const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
-   const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
-   const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
@@ -312,7 +308,7 @@ gen6_emit_MI_STORE_REGISTER_MEM(const struct ilo_dev_info *dev,
    ilo_cp_begin(cp, cmd_len);
    ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
    ilo_cp_write(cp, reg);
-   ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
+   ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
    ilo_cp_end(cp);
 }
 
@@ -323,8 +319,6 @@ gen6_emit_MI_REPORT_PERF_COUNT(const struct ilo_dev_info *dev,
 {
    const uint32_t cmd = ILO_GPE_MI(0x28);
    const uint8_t cmd_len = 3;
-   const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
-   const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
@@ -336,7 +330,7 @@ gen6_emit_MI_REPORT_PERF_COUNT(const struct ilo_dev_info *dev,
 
    ilo_cp_begin(cp, cmd_len);
    ilo_cp_write(cp, cmd | (cmd_len - 2));
-   ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
+   ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
    ilo_cp_write(cp, report_id);
    ilo_cp_end(cp);
 }
@@ -366,26 +360,14 @@ gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
    ilo_cp_begin(cp, cmd_len);
    ilo_cp_write(cp, cmd | (cmd_len - 2));
 
-   ilo_cp_write_bo(cp, 1, general_state_bo,
-                       INTEL_DOMAIN_RENDER,
-                       0);
-   ilo_cp_write_bo(cp, 1, surface_state_bo,
-                       INTEL_DOMAIN_SAMPLER,
-                       0);
-   ilo_cp_write_bo(cp, 1, dynamic_state_bo,
-                       INTEL_DOMAIN_RENDER | INTEL_DOMAIN_INSTRUCTION,
-                       0);
-   ilo_cp_write_bo(cp, 1, indirect_object_bo,
-                       0,
-                       0);
-   ilo_cp_write_bo(cp, 1, instruction_bo,
-                       INTEL_DOMAIN_INSTRUCTION,
-                       0);
+   ilo_cp_write_bo(cp, 1, general_state_bo, 0);
+   ilo_cp_write_bo(cp, 1, surface_state_bo, 0);
+   ilo_cp_write_bo(cp, 1, dynamic_state_bo, 0);
+   ilo_cp_write_bo(cp, 1, indirect_object_bo, 0);
+   ilo_cp_write_bo(cp, 1, instruction_bo, 0);
 
    if (general_state_size) {
-      ilo_cp_write_bo(cp, general_state_size | 1, general_state_bo,
-                          INTEL_DOMAIN_RENDER,
-                          0);
+      ilo_cp_write_bo(cp, general_state_size | 1, general_state_bo, 0);
    }
    else {
       /* skip range check */
@@ -393,9 +375,7 @@ gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
    }
 
    if (dynamic_state_size) {
-      ilo_cp_write_bo(cp, dynamic_state_size | 1, dynamic_state_bo,
-                          INTEL_DOMAIN_RENDER | INTEL_DOMAIN_INSTRUCTION,
-                          0);
+      ilo_cp_write_bo(cp, dynamic_state_size | 1, dynamic_state_bo, 0);
    }
    else {
       /* skip range check */
@@ -403,9 +383,7 @@ gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
    }
 
    if (indirect_object_size) {
-      ilo_cp_write_bo(cp, indirect_object_size | 1, indirect_object_bo,
-                          0,
-                          0);
+      ilo_cp_write_bo(cp, indirect_object_size | 1, indirect_object_bo, 0);
    }
    else {
       /* skip range check */
@@ -413,9 +391,7 @@ gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
    }
 
    if (instruction_size) {
-      ilo_cp_write_bo(cp, instruction_size | 1, instruction_bo,
-                          INTEL_DOMAIN_INSTRUCTION,
-                          0);
+      ilo_cp_write_bo(cp, instruction_size | 1, instruction_bo, 0);
    }
    else {
       /* skip range check */
@@ -741,8 +717,8 @@ gen6_emit_3DSTATE_VERTEX_BUFFERS(const struct ilo_dev_info *dev,
          dw |= cso->stride << GEN6_VB_STATE_DW0_PITCH__SHIFT;
 
          ilo_cp_write(cp, dw);
-         ilo_cp_write_bo(cp, start_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
-         ilo_cp_write_bo(cp, end_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
+         ilo_cp_write_bo(cp, start_offset, buf->bo, 0);
+         ilo_cp_write_bo(cp, end_offset, buf->bo, 0);
          ilo_cp_write(cp, instance_divisor);
       }
       else {
@@ -951,8 +927,8 @@ gen6_emit_3DSTATE_INDEX_BUFFER(const struct ilo_dev_info *dev,
    ilo_cp_write(cp, cmd | (cmd_len - 2) |
                     ((enable_cut_index) ? GEN6_IB_DW0_CUT_INDEX_ENABLE : 0) |
                     format);
-   ilo_cp_write_bo(cp, start_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
-   ilo_cp_write_bo(cp, end_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
+   ilo_cp_write_bo(cp, start_offset, buf->bo, 0);
+   ilo_cp_write_bo(cp, end_offset, buf->bo, 0);
    ilo_cp_end(cp);
 }
 
@@ -1527,8 +1503,7 @@ gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
    ilo_cp_begin(cp, cmd_len);
    ilo_cp_write(cp, cmd | (cmd_len - 2));
    ilo_cp_write(cp, zs->payload[0]);
-   ilo_cp_write_bo(cp, zs->payload[1], zs->bo,
-         INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+   ilo_cp_write_bo(cp, zs->payload[1], zs->bo, INTEL_RELOC_WRITE);
    ilo_cp_write(cp, zs->payload[2]);
    ilo_cp_write(cp, zs->payload[3]);
    ilo_cp_write(cp, zs->payload[4]);
@@ -1713,8 +1688,7 @@ gen6_emit_3DSTATE_STENCIL_BUFFER(const struct ilo_dev_info *dev,
    ilo_cp_write(cp, cmd | (cmd_len - 2));
    /* see ilo_gpe_init_zs_surface() */
    ilo_cp_write(cp, zs->payload[6]);
-   ilo_cp_write_bo(cp, zs->payload[7], zs->separate_s8_bo,
-         INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+   ilo_cp_write_bo(cp, zs->payload[7], zs->separate_s8_bo, INTEL_RELOC_WRITE);
    ilo_cp_end(cp);
 }
 
@@ -1734,8 +1708,7 @@ gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(const struct ilo_dev_info *dev,
    ilo_cp_write(cp, cmd | (cmd_len - 2));
    /* see ilo_gpe_init_zs_surface() */
    ilo_cp_write(cp, zs->payload[8]);
-   ilo_cp_write_bo(cp, zs->payload[9], zs->hiz_bo,
-         INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+   ilo_cp_write_bo(cp, zs->payload[9], zs->hiz_bo, INTEL_RELOC_WRITE);
    ilo_cp_end(cp);
 }
 
@@ -1765,8 +1738,6 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev,
 {
    const uint32_t cmd = ILO_GPE_CMD(0x3, 0x2, 0x00);
    const uint8_t cmd_len = (write_qword) ? 5 : 4;
-   const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
-   const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
@@ -1839,7 +1810,7 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev,
    ilo_cp_begin(cp, cmd_len);
    ilo_cp_write(cp, cmd | (cmd_len - 2));
    ilo_cp_write(cp, dw1);
-   ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
+   ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
    ilo_cp_write(cp, 0);
    if (write_qword)
       ilo_cp_write(cp, 0);
@@ -2286,26 +2257,16 @@ gen6_emit_SURFACE_STATE(const struct ilo_dev_info *dev,
    const int state_align = 32 / 4;
    const int state_len = (dev->gen >= ILO_GEN(7)) ? 8 : 6;
    uint32_t state_offset;
-   uint32_t read_domains, write_domain;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
-   if (for_render) {
-      read_domains = INTEL_DOMAIN_RENDER;
-      write_domain = INTEL_DOMAIN_RENDER;
-   }
-   else {
-      read_domains = INTEL_DOMAIN_SAMPLER;
-      write_domain = 0;
-   }
-
    ilo_cp_steal(cp, "SURFACE_STATE", state_len, state_align, &state_offset);
 
    STATIC_ASSERT(Elements(surf->payload) >= 8);
 
    ilo_cp_write(cp, surf->payload[0]);
-   ilo_cp_write_bo(cp, surf->payload[1],
-         surf->bo, read_domains, write_domain);
+   ilo_cp_write_bo(cp, surf->payload[1], surf->bo,
+         (for_render) ? INTEL_RELOC_WRITE : 0);
    ilo_cp_write(cp, surf->payload[2]);
    ilo_cp_write(cp, surf->payload[3]);
    ilo_cp_write(cp, surf->payload[4]);
diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen7.h b/src/gallium/drivers/ilo/ilo_gpe_gen7.h
index 0816fd67477..bbba9cd6b01 100644
--- a/src/gallium/drivers/ilo/ilo_gpe_gen7.h
+++ b/src/gallium/drivers/ilo/ilo_gpe_gen7.h
@@ -1036,8 +1036,8 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
    ilo_cp_write(cp, cmd | (cmd_len - 2));
    ilo_cp_write(cp, index << GEN7_SO_BUF_DW1_INDEX__SHIFT |
                     stride);
-   ilo_cp_write_bo(cp, base, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
-   ilo_cp_write_bo(cp, end, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+   ilo_cp_write_bo(cp, base, buf->bo, INTEL_RELOC_WRITE);
+   ilo_cp_write_bo(cp, end, buf->bo, INTEL_RELOC_WRITE);
    ilo_cp_end(cp);
 }
 
diff --git a/src/gallium/drivers/ilo/ilo_query.c b/src/gallium/drivers/ilo/ilo_query.c
index 46e6bf766e1..72fc1c70a70 100644
--- a/src/gallium/drivers/ilo/ilo_query.c
+++ b/src/gallium/drivers/ilo/ilo_query.c
@@ -229,7 +229,7 @@ ilo_query_alloc_bo(struct ilo_query *q, int reg_count, int repeat_count,
          intel_bo_unreference(q->bo);
 
       q->bo = intel_winsys_alloc_buffer(winsys,
-            name, size, INTEL_DOMAIN_INSTRUCTION);
+            name, size, false);
       q->reg_total = (q->bo) ? reg_total : 0;
    }
 
diff --git a/src/gallium/drivers/ilo/ilo_resource.c b/src/gallium/drivers/ilo/ilo_resource.c
index 54d6c368ae9..d312a4dffdd 100644
--- a/src/gallium/drivers/ilo/ilo_resource.c
+++ b/src/gallium/drivers/ilo/ilo_resource.c
@@ -76,13 +76,12 @@ resource_get_bo_name(const struct pipe_resource *templ)
    return name;
 }
 
-static enum intel_domain_flag
-resource_get_bo_initial_domain(const struct pipe_resource *templ)
+static bool
+resource_get_cpu_init(const struct pipe_resource *templ)
 {
    return (templ->bind & (PIPE_BIND_DEPTH_STENCIL |
                           PIPE_BIND_RENDER_TARGET |
-                          PIPE_BIND_STREAM_OUTPUT)) ?
-      INTEL_DOMAIN_RENDER : 0;
+                          PIPE_BIND_STREAM_OUTPUT)) ? false : true;
 }
 
 static void
@@ -152,11 +151,10 @@ tex_create_bo(struct ilo_texture *tex)
 {
    struct ilo_screen *is = ilo_screen(tex->base.screen);
    const char *name = resource_get_bo_name(&tex->base);
-   const enum intel_domain_flag initial_domain =
-      resource_get_bo_initial_domain(&tex->base);
+   const bool cpu_init = resource_get_cpu_init(&tex->base);
 
    tex->bo = intel_winsys_alloc_bo(is->winsys, name, tex->layout.tiling,
-         tex->layout.bo_stride, tex->layout.bo_height, initial_domain);
+         tex->layout.bo_stride, tex->layout.bo_height, cpu_init);
 
    return (tex->bo != NULL);
 }
@@ -194,7 +192,7 @@ tex_create_hiz(struct ilo_texture *tex)
 
    tex->aux_bo = intel_winsys_alloc_bo(is->winsys, "hiz texture",
          INTEL_TILING_Y, tex->layout.aux_stride, tex->layout.aux_height,
-         INTEL_DOMAIN_RENDER);
+         false);
    if (!tex->aux_bo)
       return false;
 
@@ -224,7 +222,7 @@ tex_create_mcs(struct ilo_texture *tex)
 
    tex->aux_bo = intel_winsys_alloc_bo(is->winsys, "mcs texture",
          INTEL_TILING_Y, tex->layout.aux_stride, tex->layout.aux_height,
-         INTEL_DOMAIN_RENDER);
+         false);
    if (!tex->aux_bo)
       return false;
 
@@ -357,11 +355,10 @@ buf_create_bo(struct ilo_buffer *buf)
 {
    struct ilo_screen *is = ilo_screen(buf->base.screen);
    const char *name = resource_get_bo_name(&buf->base);
-   const enum intel_domain_flag initial_domain =
-      resource_get_bo_initial_domain(&buf->base);
+   const bool cpu_init = resource_get_cpu_init(&buf->base);
 
    buf->bo = intel_winsys_alloc_buffer(is->winsys, name,
-         buf->bo_size, initial_domain);
+         buf->bo_size, cpu_init);
 
    return (buf->bo != NULL);
 }
diff --git a/src/gallium/winsys/intel/drm/intel_drm_winsys.c b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
index f94a1cb9f33..c8ae6c16a8c 100644
--- a/src/gallium/winsys/intel/drm/intel_drm_winsys.c
+++ b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
@@ -195,12 +195,7 @@ intel_winsys_create_for_fd(int fd)
 
    /*
     * No need to implicitly set up a fence register for each non-linear reloc
-    * entry.  When a fence register is needed for a reloc entry,
-    * drm_intel_bo_emit_reloc_fence() will be called explicitly.
-    *
-    * intel_bo_add_reloc() currently lacks "bool fenced" for this to work.
-    * But we never need a fence register on GEN4+ so we do not need to worry
-    * about it yet.
+    * entry.  INTEL_RELOC_FENCE will be set on reloc entries that need them.
     */
    drm_intel_bufmgr_gem_enable_fenced_relocs(winsys->bufmgr);
 
@@ -266,10 +261,8 @@ intel_winsys_alloc_bo(struct intel_winsys *winsys,
                       enum intel_tiling_mode tiling,
                       unsigned long pitch,
                       unsigned long height,
-                      uint32_t initial_domain)
+                      bool cpu_init)
 {
-   const bool for_render =
-      (initial_domain & (INTEL_DOMAIN_RENDER | INTEL_DOMAIN_INSTRUCTION));
    const unsigned int alignment = 4096; /* always page-aligned */
    unsigned long size;
    drm_intel_bo *bo;
@@ -292,12 +285,12 @@ intel_winsys_alloc_bo(struct intel_winsys *winsys,
 
    size = pitch * height;
 
-   if (for_render) {
-      bo = drm_intel_bo_alloc_for_render(winsys->bufmgr,
-            name, size, alignment);
+   if (cpu_init) {
+      bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment);
    }
    else {
-      bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment);
+      bo = drm_intel_bo_alloc_for_render(winsys->bufmgr,
+            name, size, alignment);
    }
 
    if (bo && tiling != INTEL_TILING_NONE) {
@@ -558,14 +551,37 @@ intel_bo_pread(struct intel_bo *bo, unsigned long offset,
 int
 intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
                    struct intel_bo *target_bo, uint32_t target_offset,
-                   uint32_t read_domains, uint32_t write_domain,
-                   uint64_t *presumed_offset)
+                   uint32_t flags, uint64_t *presumed_offset)
 {
+   uint32_t read_domains, write_domain;
    int err;
 
-   err = drm_intel_bo_emit_reloc(gem_bo(bo), offset,
-         gem_bo(target_bo), target_offset,
-         read_domains, write_domain);
+   if (flags & INTEL_RELOC_WRITE) {
+      /*
+       * Because of the translation to domains, INTEL_RELOC_GGTT should only
+       * be set on GEN6 when the bo is written by MI_* or PIPE_CONTROL.  The
+       * kernel will translate it back to INTEL_RELOC_GGTT.
+       */
+      write_domain = (flags & INTEL_RELOC_GGTT) ?
+         I915_GEM_DOMAIN_INSTRUCTION : I915_GEM_DOMAIN_RENDER;
+      read_domains = write_domain;
+   } else {
+      write_domain = 0;
+      read_domains = I915_GEM_DOMAIN_RENDER |
+                     I915_GEM_DOMAIN_SAMPLER |
+                     I915_GEM_DOMAIN_INSTRUCTION |
+                     I915_GEM_DOMAIN_VERTEX;
+   }
+
+   if (flags & INTEL_RELOC_FENCE) {
+      err = drm_intel_bo_emit_reloc_fence(gem_bo(bo), offset,
+            gem_bo(target_bo), target_offset,
+            read_domains, write_domain);
+   } else {
+      err = drm_intel_bo_emit_reloc(gem_bo(bo), offset,
+            gem_bo(target_bo), target_offset,
+            read_domains, write_domain);
+   }
 
    *presumed_offset = gem_bo(target_bo)->offset64 + target_offset;
 
diff --git a/src/gallium/winsys/intel/intel_winsys.h b/src/gallium/winsys/intel/intel_winsys.h
index 679f24817b8..bc18bb69be5 100644
--- a/src/gallium/winsys/intel/intel_winsys.h
+++ b/src/gallium/winsys/intel/intel_winsys.h
@@ -44,14 +44,10 @@ enum intel_exec_flag {
 };
 
 /* this is compatible with i915_drm.h's definitions */
-enum intel_domain_flag {
-   INTEL_DOMAIN_CPU           = 0x00000001,
-   INTEL_DOMAIN_RENDER        = 0x00000002,
-   INTEL_DOMAIN_SAMPLER       = 0x00000004,
-   INTEL_DOMAIN_COMMAND	      = 0x00000008,
-   INTEL_DOMAIN_INSTRUCTION   = 0x00000010,
-   INTEL_DOMAIN_VERTEX        = 0x00000020,
-   INTEL_DOMAIN_GTT           = 0x00000040,
+enum intel_reloc_flag {
+   INTEL_RELOC_FENCE          = 1 << 0,
+   INTEL_RELOC_GGTT           = 1 << 1,
+   INTEL_RELOC_WRITE          = 1 << 2,
 };
 
 /* this is compatible with i915_drm.h's definitions */
@@ -126,7 +122,7 @@ intel_winsys_read_reg(struct intel_winsys *winsys,
  * \param tiling           Tiling mode.
  * \param pitch            Pitch of the bo.
  * \param height           Height of the bo.
- * \param initial_domain   Initial (write) domain.
+ * \param cpu_init         Will be initialized by CPU.
  */
 struct intel_bo *
 intel_winsys_alloc_bo(struct intel_winsys *winsys,
@@ -134,7 +130,7 @@ intel_winsys_alloc_bo(struct intel_winsys *winsys,
                       enum intel_tiling_mode tiling,
                       unsigned long pitch,
                       unsigned long height,
-                      uint32_t initial_domain);
+                      bool cpu_init);
 
 /**
  * Allocate a linear buffer object.
@@ -143,10 +139,10 @@ static inline struct intel_bo *
 intel_winsys_alloc_buffer(struct intel_winsys *winsys,
                           const char *name,
                           unsigned long size,
-                          uint32_t initial_domain)
+                          bool cpu_init)
 {
    return intel_winsys_alloc_bo(winsys, name,
-         INTEL_TILING_NONE, size, 1, initial_domain);
+         INTEL_TILING_NONE, size, 1, cpu_init);
 }
 
 /**
@@ -275,8 +271,7 @@ intel_bo_pread(struct intel_bo *bo, unsigned long offset,
 int
 intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
                    struct intel_bo *target_bo, uint32_t target_offset,
-                   uint32_t read_domains, uint32_t write_domain,
-                   uint64_t *presumed_offset);
+                   uint32_t flags, uint64_t *presumed_offset);
 
 /**
  * Return the current number of relocations.