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intel/eu: force stride of 2 on NULL register for Byte instructions 

The hardware only allows a stride of 1 on a Byte destination for raw
byte MOV instructions. This is required even when the destination
is the NULL register.

Rather than making sure that we emit a proper NULL:B destination
every time we need one, just fix it at emission time.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Iago Toral Quiroga 2018-11-07 12:08:02 +01:00 committed by Juan A. Suarez Romero
parent ce68a061de
commit fb990bd76e
1 changed files with 11 additions and 0 deletions
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11
src/intel/compiler/brw_eu_emit.c
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@ -94,6 +94,17 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
else if (dest.file == BRW_GENERAL_REGISTER_FILE)
assert(dest.nr < 128);
/* The hardware has a restriction where if the destination is Byte,
* the instruction needs to have a stride of 2 (except for packed byte
* MOV). This seems to be required even if the destination is the NULL
* register.
*/
if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
dest.nr == BRW_ARF_NULL &&
type_sz(dest.type) == 1) {
dest.hstride = BRW_HORIZONTAL_STRIDE_2;
}
gen7_convert_mrf_to_grf(p, &dest);
if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS ||