From fb990bd76eb02425d1982d682716ebe766b536b8 Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Wed, 7 Nov 2018 12:08:02 +0100 Subject: [PATCH] intel/eu: force stride of 2 on NULL register for Byte instructions The hardware only allows a stride of 1 on a Byte destination for raw byte MOV instructions. This is required even when the destination is the NULL register. Rather than making sure that we emit a proper NULL:B destination every time we need one, just fix it at emission time. Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_eu_emit.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index f5318e37f58..a271621393d 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -94,6 +94,17 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) else if (dest.file == BRW_GENERAL_REGISTER_FILE) assert(dest.nr < 128); + /* The hardware has a restriction where if the destination is Byte, + * the instruction needs to have a stride of 2 (except for packed byte + * MOV). This seems to be required even if the destination is the NULL + * register. + */ + if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE && + dest.nr == BRW_ARF_NULL && + type_sz(dest.type) == 1) { + dest.hstride = BRW_HORIZONTAL_STRIDE_2; + } + gen7_convert_mrf_to_grf(p, &dest); if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS ||